'",-,
Figure
7-5
Figure
7-6
Figure
7-7
Figure
7-8
Figure
7-9
Figure
7-10
Figure
7-11
Figure
8-1
Figure
8-2
Figure
8-3
Figure
8-4
Figure
8-5
Figure
8-6
Figure
8-7
Figure
8-8
Figure
9-1
Figure
9-2
Figure
9-3
Figure
9-4
Figure
9-5
Figure
9-6
Figure
9-7
Figure
9-8
Figure
9-9
Figure
9-10
Figure
9-11
Figure
9-12
Figure
9-13
Figure
9-14
Figure
9-15
Figure
9-16
Figure
9-17
Figure
9-18
Figure
9-19
Figure
9-20
Figure
9-21
Figure
9-22
Figure
9-23
Figure
10-1
Figure
10-2
Figure
10-3
Figure
10-4
Figure
10-5
Figure
10-6
Figure
10-7
Figure
10-8
Figure
10-9
Z8681
Port
0
Memory
Operation
Z8682
Port
0
Memory
Operation
External
Stack
Operation
• • •
Port
3 Data
Memory
Operation
• •
•
7-3
•
7-4
• 7-5
• • 7-5
Extended
Bus
Timing • • • • • • •
7-5
Z8681
Port
0 and 1 Reset
Conditions
• • • • • • • • • • • • • •
••
7-6
Z8682
Ports
0 and 1 Reset
Conditions
••••••••••••••••
7-6
Reset Timing
Power-Up Reset
Circuit
Z8
Clock
Circuit
Crystal/Ceramic
Resonator
Oscillator
External
Clock
Interface
Battery-Backed
Register
Supply
Normal
and
Test
Mode
Flow
Voltage
Waveform
for
Test
Mode
I/O
Port
and
Port
Mode
Registers
Ports
0,
1,
and 2 Block Diagram
Port
0 I/O
Operation
• • • •
Port
0 Handshake
Operation
•
Port
0 • • • • • • • • • • •
Port
1 I/o
Operation
• • • •
Port
Port
Handshake
Operation
•
Port
2 I/O
Operation
• • •
Port
3 Handshake
Operation
•
Port
2 • • • • • • • • • • •
Port
2 Open-Drain Outputs
Port
3 Block Diagram
Port
3 I/O
Operation
•
Z8
Input
Handshake • •
•
8-2
• 8-3
• 8-3
• 8-3
• 8-3
•
8-4
• •
8-4
•••••
8-5
• • 9-1
9-2
• •
9-3
•
9-3
• 9-3
•
9-4
• •
9-4
•
•••••
9-4
• • 9-5
•
9-5
• •
9-5
• 9-6
•
9-6
•
9-7
• 9-8
Z8
Output Handshake • • • • • • • • • • • • •
9-9
Input
Strobed Handshake
using
Port
2 • • • • • • • • • • • • 9-9
Output Strobed Handshake
using
Port
2 •
9-9
Z8601/11
Ports
0 and 1
Reset.
• • • • • • 9-10
Z8681
Ports
0 and 1 Reset • • • • • • • 9-10
Z8682
Ports
0 and 1 Reset • • • • • • • • • • • • • • • • • • •
••
9-10
Port
2
Reset.
• • • • • • • • • • • • • 9-11
Port
3
Reset.
• • • • • • • • • 9-11
Interrupt
Control
Registers
•••••
• •
Interrupt
Block Diagram • • • • • • • •
Interrupt
Sources
IRQO-IRQ2
Block Diagram
Interrupt
Source
IRQ3
Block Diagram
IRQ
Register
Logic • • • • • • • • • • •
Interrupt
Request
Timing.
• • • •
••••••
Interrupt
Priority
Register
•••••
Interrupt
Mask
Register
•••••
Interrupt
Request
Register
• •
• 10-1
• 10-1
• 10-2
••
10-2
• 10-3
• 10-3
• 10-4
• 10-5
• 10-5
ix