ZiLOG Z8 Technical Manual

Counter/Timers
11.5.3 Triggered Input Mode
The TIN Triggered Input mode (TMR bits Os and
04 set to 1 and a respectively) causes T1 to start
counting as the result of an external event
(Figure
11-17). T1 is then loaded and clocked by
the internal timer clock following the first High-
to-Low
transition on the T IN input. Subsequent
T
IN transitions do not affect T 1. In the Sin-
gle-Pass mode, the Enable bit is reset whenever T1
reaches its end-of-count. Further T IN transi-
tions will have no effect on T 1 until software
sets the Enable Count bit again. In Continuous
mode, once T1 is triggered counting continues
until software resets the Enable Count bit.
Interrupt request IRQS is generated when T1
reaches its end-of-count.
11.5.4 Retriggerable Input Mode
The TIN Retriggerable Input mode (TMR bits Os
and 04 both set to 1) causes T1 to load and start
counting on every occurrence of a High-to-Low
transition on TIN (Figure 11-17). Interrupt
request IRQS will be generated if the programmed
time interval (determined by T1 prescaler and
counter/timer register initial values) has elapsed
since the last High-to-L9W transition on TIN.
In Single-Pass mode, the end-of-count resets the
Enable Count bit. Subsequent TIN transitions
will not cause T1 to load and start counting until
software sets the Enable Count bit again. In Con-
tinuous mode, counting continues once T1 is trig-
gered until software resets the Enable Count bit.
When enabled, each High-to-Low ,TIN transition
causes T1 to reload and restart counting. Inter-
rupt request IRQS is generated on every end-of-
count.
11.6 CASCADING COUNTER/TIMERS
For some applications, it may be necessary to mea-
sure a time interval greater than a single coun-
ter/timer can measure. In this case, T IN and
TOUT can be used to cascade TO and T1 as a sin-
gle unit (Figure 11-18). TO should be configured
to operate in Continuous mode and to drive
TOUT. TIN should be configured as an external
clock input to T 1 and wired back to TOUT. On
every other TO end-of-count, TOUT undergoes a
High-to-Low transition which causes T 1 to count.
T1 can operate in either Single-Pass or Continuous
mode. Each time T 1's end-of-count is reached,
interrupt request IRQS is generated. Interrupt
requests IRQ2 (TIN High-to-Low transitions) and
11-8
IRQ4 (TO end-of-count) are also generated but are
most likely of no importance in this configuration
and should be disabled.
11.7 RESET CONDITIONS
After a hardware reset, the counter/timers are
disabled and the contents of both the counter/
timer registers and the prescaler modulos are
undefined. However, the counting modes are
configured for Single-Pass and T l' s clock source
is set for external. T IN is set for External
Clock mode, and the TOUT mode is off. Figures
11-19 through 11-22 show the binary reset values
of the Prescaler, Counter/Timer, and Timer Mode
registers.
R242 T1
Counter/Timer 1 Register
(% F2; Read/Write)
R244 TO
Counter/Timer 0 Register
(% F4; Read/Write)
L INITIAL VALUE WHEN WRITTEN
(RANGE 1·256 DECIMAL, 01·00 HEX)
CURRENT VALUE WHEN READ
Figure 11-19. Counter/Timer Reset
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
~
COUNTMODE
1 = T1 MODULO·N
o = T1 SINGLE·PASS
CLOCK SOURCE
1 = T1 INTERNAL
o = T1 EXTERNAL (TIN)
PRESCALER MODULO
L....-------(RANGE: 1-64 DECIMAL
01-00 HEX)
Figure 11-20. Prescaler 1 Register Reset
3047 -021, 3047-022

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English