ZiLOG Z8 Technical Manual

12.1 INTRODUCTION
The Z8 microcomputer contains an on-board
full-duplex receiver/transmitter for asynchronous
data communications. The receiver/transmitter
consists of a Serial I/O register 510 (%F1) and
its associated control logic (Figure 12-1). The
510 is actually two registers--the receiver buffer
and the transmitter buffer--which are used in
conjunction with counter/timer TO and Port 3 I/O
lines P30 (input) and P37 (output). Counter/timer
fO provides the clock input for control of the
data rates.
Configuration of the ser ial I/O is controlled by
the Port 3 Mode register, P3M. The Z8 always
transmits 8 bits between the start and stop bits;
that is, 8 data bits or 7 data bits and 1 parity
bit. Odd parity generation and detection is
supported.
The Serial I/O register and its associated Mode
Control registers are mapped into the register
file as shown in Figure 12-2. This organization
Chapter 12
Serial 1/0
allows the software to access the serial I/O as
general-purpose registers, eliminating the need
for special instructions.
12.2 BIT RATE GENERATION
When Port 3 Mode register bit D6 is set to 1, the
serial I/O is enabled and TO automatically becomes
the bit rate generator (Figure 12-3). TO'S end-
of-cou~t signal no longer generates interrupt
request IRQ4; instead, the signal is used as the
input to the divide-by-16 counters (one each for
the receiver and the transmitter) which clock the
data stream.
The divide chain that generates the bit rate is
shown in Figure 12-4. The bit rate is given by
the following equation:
bit rate = XTAL frequency/(2 x 4 x p x t x 16)
where p and t
are the initial values in the
Prescaler and Counter/Timer registers,
respectively.
J
INTERNAL DATA BUS
J
P3
SERIAL
1/0 CLOCK
(FROM
TO)
0-
-
READ%FO ~ 11
RECEIVER
TRANSFER
BUFFER
WRITE %FO
11 ~
RECEIVER
TRANSMITTER
SERIAL
CHAR
IN
~~
SHIFT
f----
DETECT
f-
SHIFT
REGISTER
r
REGISTER
~
t SHIFT
SHIFT
CLOCK
CLOCK
RESET
START
PARITY
BIT
'"'-
CHECK
+16
DETECT
~ START
CLOCK
-
... 6
CONTROL
t STOP
Figure 12-1. Serial I/O Block Diagram
STOP
BIT
IRa4
DETECT
MARK
1---
~D-
SERIAL
OUT
I-
P
3
7
PARITY
GEN
IRa3
3047-068 12-1

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English