ZiLOG Z8 Technical Manual

DECW
Decrement Word
DECW dst
Instruction For.at:
Cycles
OPC
(Hex)
Address Mode
dst
~ ______ OP_C ______ ~I I~ _______ d_st ______ ~
10
80
81
RR
IR
Operation:
Flags:
EXBq)le:
Note:
5-18
dst <-- dst - 1
The contents of the destination location (which rust be an even address) and the
operand following that location are treated as a single 16-bit value which is
decremented by one.
C: Unaffected
Z: Set if the result is zero; cleared otherwise
V: Set if arithmetic overflow occurred; cleared otherwise
5: Set if the result is negative; cleared otherwise
H: Unaffected
D: Unaffected
If working register 0 contains %30 (48 decimal) and registers 48-49 contain the value
%FAF3, the statement
DECW aRO
leaves the value %FAF2 in· registers 48 and 49. The Z and V flags are cleared and S
is set.
When used to specify a 4-bit working-register pair address, address modes RR or IR
use the format:
E
dst

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English