ZiLOG Z8 Technical Manual

OR dst,src
Instruction foraat:
OPC
OPC
OPC
Operation:
flags:
Example:
Note:
OR
Logical Or
OPC
Address Mode
Cycles
(Hex)
dst src
I
I
dst src
6 42
r
r
6
43
r
Ir
I
I
src
I
I
dst
10
44
R
R
10
45 R IR
I
I
dst
I
I
src
10 46
R 1M
10
47 IR
1M
dst <-- dst OR src
The source operand is logically ORed with the destination operand and the result is
stored in the destination. The contents of the source are not affected. The OR
operation results in a one bit being stored whenever either of the corresponding bits
in the two operands is 1; otherwise a 0 bit is stored.
C: Unaffected
Z: Set if result is zero; cleared otherwise
V: Always reset to 0
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
0: Unaffected
If the source operand is the immediate value %7B (01111011) and the register named
TARGET contains %C3 (11000011), the statement
OR TARGET,I%7B
leaves the value %FB (11111011) in register TARGET. The Z and V flags are cleared
and S is set.
When used to specify a 4-bit working-register address, address modes Rand IR use the
format:
E
src/dst
5-33

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English