ZiLOG Z8 - Page 78

SRA
Shift Right Arithmetic
SRA dat
Instruction r ormat:
Cycles
OPC
(Hex)
Address Mode
dot
~ ______ OP_C ______ ~I I~ _______ ds_t ______ ~
6
6
DO
01
R
IR
Operation:
Flags:
EX&qlle:
Note:
5-44
dst(7) <-- dst(7)
C <-- dst(O)
dst(n) <-- dst(n + 1) n = 0 - 6
An arithmetic shift right one bit position ia performed on the destination operand.
Bit 0 replaces the C flag. Bit 7 (the Sign bit) is unchanged, and its value is also
shifted into bit position 6.
7
o
c: Set if the bit shifted from the least significant bit position was 1; i.e., bit 0
was 1
Z: Set if the result is zero; cleared otherwise
V: Always reset to 0
5: Set if the result is negative; cleared otherwise
H: Unaffected
0: Unaffected
If the register named SHIFTER contains ~BB (10111000), the statement
SRA SHIFTER
resets the C flag to 0 and leaves the value %DC (11011100) in register SHIFTER. The
S flag is set to 1.
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E
dst