ZiLOG Z8

Chapter 11. Counter /T imers
11.1 Introduction
11.2 Prescalers and Counter/Timers ••
11.3 Counter/Timer Operation
11.3.1 Load and Enable Count Bits
11.3.2 Prescaler Operations
11.4 TOUT Modes •••
11.5 TIN Modes.
11.5.1 External Clock Input Mode.
11.5.2 Gated Internal Clock Mode.
11.5.3 Triggered Input Mode
11.5.4 Retriggerable Input Mode
11.6 Cascading Counter/Timers.
11.7 Reset Conditions
Chapter 12. Serial I/O
12.1 Introduction
12.2 Bit Rate Generation
12.3 Receiver Operation.
12.4
12.5
12.3.1 Receiver Shift Register.
12.3.2 Overwrites
12.3.3 Framing Errors
12.3.4 Parity
Transmitter Operation •
12.4.1 Overwrites
12.4.2 Parity
Reset Conditions
Appendix A. Pin Descriptions and functions
A.1 Development Device (Z8612)
A.2
Protopack Emulator (Z8603/13)
Appendix B.
Control Registers
Appendix C. Opcode Hap • • • •
11-1
• 11-2
11-3
11-3
11-3
• 11-4
• 11-5
11-6
11-6
11-8
• 11-8
• 11-8
•• 11-8
••• 12-1
• 12-1
• 12-3
12-3
• 12-4
• 12-4
• 12-4
12-4
• 12-5
• 12-5
12-6
• A-1
• A-1
B-1
C-1
11
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