drop DV
C
on series capacitor lags the fault current by 90 degrees. Note that line impedance
X
L1
could be divided into two parts: one between the IED point and the capacitor and one
between the capacitor and the fault position. The resulting voltage V
M
in IED point is this
way proportional to sum of voltage drops on partial impedances between the IED point
and the fault position F, as presented by
( )
M F L1 C
V I j X X= × -
EQUATION1995-ANSI V1 EN (Equation 52)
en06000605_ansi.vsd
~
21
XS
X
L1
IF
V
V
M
Source
Fault voltage
Pre -fault voltage
X
C
Source voltage
V’
M
With bypassed
capacitor
With inserted
capacitor
F
X
ANSI06000605 V1 EN
Figure 81: Voltage inversion on series compensated line
en06000606_ansi.vsd
I
F
V
S
V
’
M
=
x
V
L
x
V
S
I
F
x
V
L
V
S
x
V
C
V
M
x
V
S
With bypassed
capacitor
With inserted
capacitor
ANSI06000606 V1 EN
Figure 82: Phasor diagrams of currents and voltages for the bypassed and inserted
series capacitor during voltage inversion
It is obvious that voltage V
M
will lead the fault current I
F
as long as X
L1
> X
C
. This
situation corresponds, from the directionality point of view, to fault conditions on line
Section 8 1MRK 506 369-UUS -
Impedance protection
182 Line distance protection REL670 2.2 ANSI
Application manual
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