ABB Relion 670 series - Page 410

en06000605_ansi.vsd
~
21
XS
X
L1
IF
V
V
M
Source
Fault voltage
Pre -fault voltage
X
C
Source voltage
V’
M
With bypassed
capacitor
With inserted
capacitor
F
X
ANSI06000605 V1 EN
Figure 201: Voltage inversion on series compensated line
en06000606_ansi.vsd
I
F
V
S
V
’
M
=
x
V
L
x
V
S
I
F
x
V
L
V
S
x
V
C
V
M
x
V
S
With bypassed
capacitor
With inserted
capacitor
ANSI06000606 V1 EN
Figure 202: Phasor diagrams of currents and voltages for the bypassed and inserted
series capacitor during voltage inversion
It is obvious that voltage V
M
will lead the fault current I
F
as long as X
L1
> X
C
. This
situation corresponds, from the directionality point of view, to fault conditions on line
without series capacitor. Voltage V
M
in IED point will lag the fault current I
F
in case
when:
L1 C S L1
X X X X< < +
EQUATION1902 V1 EN (Equation 363)
Where
X
S
is the source impedance behind the IED
Section 8 1MRK 506 369-UUS -
Impedance protection
404 Line distance protection REL670 2.2 ANSI
Application manual