ABB ret650 - Page 255

IL1
|DI|
a
b
a>b
DI<
One cycle
delay
UL1
a
b
a>b
One cycle
delay
DU>
|DU|
a
b
a>b
t
20 ms
t
1.5 cycle
AND
DUDI detection Phase 1
UPh>
DUDI detection Phase 2
Same logic as for phase 1
IL2
UL2
DUDI detection Phase 3
Same logic as for phase 1
IL3
UL3
a
b
a<b
UL1
IL1
a
b
a>b
IPh>
AND
AND
CBCLOSED
OR
OR
AND
a
b
a<b
UL2
IL2
a
b
a>b
AND
AND
OR
OR
AND
a
b
a<b
UL3
IL3
a
b
a>b
AND
AND
OR
OR
AND
OR
FuseFailDetDUDI
DUDI Detection
IEC10000034-1-en.vsd
IEC10000034 V1 EN
Figure 112: Simplified logic diagram for DU/DI detection part
1MRK 504 135-UEN A Section 11
Secondary system supervision
249
Technical manual