ABB UniGear Digital - ESSAILEC RJ45 Test Block

To Next Page

To Previous Page

20 1VLG5 00007 E

ESSAILEC® RJ45 test block

The test block is used for efficient testing of protection and control relay with sensor inputs

during regular maintenance. The test block is flush mounting type on the low voltage com-

partment door and its vertical layout is recommended. The testing of protection and control

relay’s sensor inputs is possible without opening the low voltage compartment door. One

test block is intended for one phase and it consists of a socket, a lid and a plug.

Figure 19: ESSAILEC

RJ45 test block

Figure 20: Low Voltage Compartment door with ESSAILEC

RJ45 test blocks

The socket is covered during Normal operation by the lid. For testing, the lid is removed and

replaced by the test plug.

Figure 21: The testing (only one phase is shown)

ESSAILEC® Trip or Polarity range test block

A test block allows the testing without circuit breaker tripping.

Main Page

Table of Contents5
Introduction13
This Manual13
Intended Users13
Unigear Digital14
Figure 1: Unigear Digital and Its Key Components14
Sensors15
Table 1: Sensor Product Portfolio for Unigear Digital15
Current Sensors16
Figure 2: Current Sensor KECA 80 C104 / KECA 80 C16516
Figure 3: Current Sensor KECA 80 C184 / KECA 80 C21617
Figure 4: Current Sensor KECA 250 B118
Voltage Sensors19
Figure 5: Voltage Sensor KEVA 17.5 B2019
Figure 6: Voltage Sensor KEVA 24 B2020
Figure 7: Coupler Adapter AR5 Utilized with Relion21
Figure 8: Connector Pins Assignment of a Current Sensor Plug22
Figure 9: Connector Pins Assignment of a Voltage Sensor Plug22
Protection Relays23
Table 2: Protection Relay Key Functionality Overview for Unigear Digital23
Figure 10: Functionality Overview of REF615 Standard Configuration G24
Figure 11: Functionality Overview of REF615 Standard Configuration L25
Figure 12: Functionality Overview of REM615 Standard Configuration D26
Figure 13: Functionality Overview of RED615 Standard Configuration E27
Figure 14: Functionality Overview of REF620 Standard Configuration B28
Figure 15: Functionality Overview of REM620 Standard Configuration B29
Figure 16: Protection and Control REX64030
Figure 17: Overview of RIO600 Connection31
Figure 18: RIO600 Communicating Analog Signals for the Panel Meters31
Figure 19: ESSAILEC ® RJ45 Test Block32
Figure 20: Low Voltage Compartment Door with ESSAILEC ® RJ45 Test Blocks32
Figure 21: the Testing (Only One Phase Is Shown)32
Iec 6185033
Figure 22: Switchgear with Sensor Measurement33
Figure 23: Switchgear with Sensor Measurement and Process Bus Application of Voltage Sharing and Synchrocheck34
Switchgear Type Overview35
Figure 24: Unigear ZS1 Digital (17.5 Kv, 4 000 A, 50 Ka)35
Table 3: Overview of Unigear Digital in Unigear Switchgear Family35
Figure 25: Unigear ZS1 Digital (24 Kv, 3 150 A, 31.5 Ka)36
Figure 26: Unigear 550 Digital (12 Kv, 1 250 A, 31.5 Ka)36
Figure 27: Unigear 500R Digital (17.5 Kv, 2 000 A, 31.5 Ka)37
Figure 28: Unigear MCC Digital (12 Kv, 400 A, 50 Ka)37
Engineering38
Sensors38
Current Sensors38
Figure 29: Example of a Current Sensor Label38
Figure 30: Example of Setting the Correction Factors for Current Sensor in PCM60038
Figure 31: Single Line Diagram39
Figure 32: Example of Setting Values for Current Sensor in PCM60040
Figure 33: Example of Parameter Setting for PHIPTOC1 Start Value in PCM60040
Figure 34: Current Sensor with Unique Physical Polarity41
Table 4: Maximum Current Start and Protection Setting Values41
Figure 35: Polarity Setting for Current Sensors in Incoming Feeder42
Figure 36: Example of Polarity Setting for Current Sensor in PCM60042
Voltage Sensors43
Figure 37: Example of a Voltage Sensor Label43
Figure 38: Example of Setting the Correction Factors for Voltage Sensor in PCM60043
Figure 39: Single Line Diagram44
Figure 40: Example of Setting Values for Voltage Sensor in PCM60044
Documentation45
Figure 41: Example of a Network Overview Diagram45
Figure 42: Example of a Logic Diagram for Interconnection between Panels45
Figure 43: Example of a Sampled Measured Value Diagram46
Station Bus (GOOSE)47
Figure 44: Creating a New GOOSE Data Set and Its Entries48
Figure 45: GOOSE Control Block Properties48
Figure 46: GOOSE Control Block Editor (1- Receiver #1, 2- Receiver #2, 3 - Sender)50
Figure 47: Selecting Show IED Capabilities Tab50
Figure 48: Editing 615 Series Capabilities51
Figure 49: Creating a New GOOSE Data Set and Its Entries51
Figure 50: Naming a GOOSE Control Block52
Figure 51: GCB Client52
Figure 52: Adding a GOOSERCV Function Block in the Application Configuration Tool53
Figure 53: Creating GOOSERCV Block Connection to a New Variable53
Figure 54: Signal Matrix53
Process Bus (SMV)54
Figure 55: Example of Process Bus Application of Voltage Sharing and Synchro-Check54
Figure 56: Example of Process Bus Application of Voltage Sharing Redundancy and Synchro Check54
Figure 57: Adding a SMSENDER Block in the Application Configuration Tool55
Figure 58: Adding a ULTVTR1 Block in the Application Configuration Tool55
Figure 59: Time Parameter Setting Dialog in PCM60056
Figure 60: Configuring the SMV Senders and Receivers57
Figure 61: Changing the Sampled Measured Value Control Block Attributes58
Figure 62: Selecting Show IED Capabilities Tab59
Figure 63: Editing 615 Series Capabilities60
Figure 64: Sampled Value Control Block60
Figure 65: Connecting the SMV Senders and Receivers60
Figure 66: Receiving All Phase Voltages and Residual Voltage Using SMV61
Figure 67: Receiving Line Voltage for Synchrocheck Functionality Using SMV61
Figure 68: Application Configuration Tool Logic Examples for the SMV Fail Save Operation62
Figure 69: SMV Max Delay Setting in PCM60063
Table 5: Topology-Dependent SMV Max Delay Setting63
Ethernet64
Requirements64
Technology65
Figure 70: FTP Patch Cable Terminated with RJ-45 Connectors65
Figure 71: Fiber Optic Patch Cable Terminated with LC Connectors65
Figure 72: LC Connectors66
Figure 73: Communication Module with Single Ethernet Connector66
Figure 74: Communication Modules with Multiple Ethernet Connectors67
Table 6: Recommended Managed Ethernet Switches Overview for Unigear Digital68
Figure 75: Example of Managed Ethernet Switches from AFS Family69
Figure 76: 1 - Fast Ethernet Fiber Optic SFP Module, 2 - Gigabit Ethernet Fiber Optic SFP Module69
Figure 77: Installed SFP Module in Managed Ethernet Switch AFS67769
Figure 78: Example of Satellite Controlled Clock from Tekron with Optional Accessories70
Figure 79: Example of Satellite Controlled Clock from Meinberg71
Figure 80: Low Voltage Compartment of Unigear Panel71
Topologies72
Figure 81: RSTP Ring Redundant Structure72
Figure 82: MRP / E-MRP Ring Redundant Structure73
Figure 83: Single Network Using RSTP / E-MRP73
Figure 84: PRP Networks Using RSTP / E-MRP74
Figure 85: HSR Network75
Figure 86: HSR Network with Redboxes75
Figure 87: Combined PRP and HSR Networks76
Table 7: Comparison of Network Topologies77
Ethernet Traffic Estimation78
Naming Convention to Identify Protection Relays79
IP Address Allocation79
Time Synchronization80
Figure 88: Example of an Allocation of Device IP Addresses80
Figure 89: Example of IEEE 1588-Time Synchronization Via the Ethernet Network80
Table 8: C37.238 Power Profile Key Parameters81
Figure 90: IEEE 1588 Time Synchronization Scheme for HSR-PRP Networks82
Figure 91: IEEE 1588 Time Synchronization Scheme for PRP Networks82
Traffic Segregation83
Figure 92: Example of Traffic Segregation Via Building Virtual Lans83
Figure 93: Virtual Lans Allocation in PRP-RSTP Networks83
Figure 94: Virtual Lans Allocation in HSR-PRP Networks84
Protection Relays85
Figure 95: Communication Parameter Setting Dialog85
Figure 96: Adding RCHLCCH and SCHLCCH Blocks in the Application Configuration Tool86
Figure 97: Status of Ethernet Rear Port Displayed Via ITT SA Explorer (on Top and on Bottom)87
Managed Ethernet Switches88
Figure 98: AFS Switch Screen88
Figure 99: Login Window88
Figure 100: Network Parameters Dialog89
Figure 101: Port Configuration Dialog89
Figure 102: Load/Save Dialog90
Figure 103: PTP Global Dialog91
Figure 104: PTP Version 2 (Transparent Clock) Global Dialog91
Figure 105: PTP Version 2 (Transparent Clock) Port Dialog92
Figure 106: Switching Global Dialog in Afs67X (on Top) and Afs66X (on Bottom)93
Figure 107: VLAN Global Dialog in Afs67X94
Figure 108: VLAN Static Dialog94
Figure 109: VLAN Port Dialog95
Figure 110: Spanning Tree Global Dialog96
Figure 111: Spanning Tree Ports Dialog96
Figure 112: E-MRP Ring Redundancy Dialog97
Figure 113: Example of AFS660 Front View98
Figure 114: Switching Global Dialog98
Figure 115: PRP Configuration Dialog99
Figure 116: HSR Configuration Dialog100
Figure 117 : IEC61850-MMS Configuration Dialog100
Satellite Controlled Clock101
Figure 118: Tekron Clock Configuration Tool101
Figure 119: Basic Setting Dialog102
Figure 120: PTP Setting Dialog102
Figure 121: Port Configuration Dialog103
Figure 122: PTP Setting Dialog103
Figure 123: PTP Global Settings Dialog104
Figure 124: PTP Network Settings Dialog105

ABB UniGear Digital - ESSAILEC RJ45 Test Block

Table of Contents

Other manuals for ABB UniGear Digital

Related product manuals