12.3 ADC operation................................................................................................................... 110
12.4 Register map ..................................................................................................................... 111
12.5 Register description .......................................................................................................... 111
13 I2C .............................................................................................................................................. 114
13.1 Block diagram ................................................................................................................... 114
13.2 Bit transfer ......................................................................................................................... 115
13.3 Start/ repeated start/ stop ................................................................................................. 115
13.4 Data transfer ..................................................................................................................... 116
13.5 Acknowledge ..................................................................................................................... 116
13.6 Synchronization/ Arbitration .............................................................................................. 117
13.7 Block operation ................................................................................................................. 119
13.7.1 I2C block initialization process ............................................................................. 119
13.7.2 I2C interrupt Service ............................................................................................. 120
13.7.3 Master transmitter ................................................................................................ 121
13.7.4 Slave Receiver ..................................................................................................... 123
13.8 Register map ..................................................................................................................... 124
13.9 I2C register description ..................................................................................................... 125
14 USART ....................................................................................................................................... 129
14.1 Block diagram ................................................................................................................... 130
14.2 Clock generation ............................................................................................................... 131
14.3 External clock (XCK) ......................................................................................................... 132
14.4 Synchronous mode operation ........................................................................................... 132
14.5 Data format ....................................................................................................................... 133
14.6 Parity bit ............................................................................................................................ 134
14.7 USART transmitter ............................................................................................................ 134
14.7.1 Sending Tx data ................................................................................................... 134
14.7.2 Transmitter flag and interrupt ............................................................................... 134
14.7.3 Parity generator .................................................................................................... 135
14.7.4 Disabling transmitter ............................................................................................. 135
14.8 USART receiver ................................................................................................................ 135
14.8.1 Receiving Rx data ................................................................................................ 135
14.8.2 Receiver flag and interrupt ................................................................................... 136
14.8.3 Parity checker ....................................................................................................... 137
14.8.4 Disabling receiver ................................................................................................. 137
14.8.5 Asynchronous data reception ............................................................................... 137
14.9 SPI mode .......................................................................................................................... 139
14.9.1 SPI clock formats and timing ................................................................................ 139
14.10 Receiver time out (RTO) ................................................................................................... 142
14.11 Register map ..................................................................................................................... 143
14.12 Register description .......................................................................................................... 144
14.13 Baud rate settings (example) ............................................................................................ 151
14.14 0% error baud rate ............................................................................................................ 153
15 Power down operation ............................................................................................................... 154
15.1 Peripheral operation in IDLE/ STOP mode ....................................................................... 154
15.2 IDLE mode ........................................................................................................................ 155
15.3 STOP mode ...................................................................................................................... 155
15.4 Released operation of STOP mode .................................................................................. 156
15.5 Register map ..................................................................................................................... 158
15.6 Register description .......................................................................................................... 158
16 Reset .......................................................................................................................................... 159
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