Abov A96G174 - Page 46

6. I/O ports A96G174/A96S174 User’s manual
46
P0DB (P0 De-bounce Enable Register): DEH
7
6
5
4
3
2
1
0
DBCLK1
DBCLK0
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
DBCLK[1:0]
Configure De-bounce Clock of Port
DBCLK1
DBCLK0
Description
0
0
fx/1
0
1
fx/4
1
0
fx/4096
1
1
LSIRC (128kHz)
P07DB
Configure De-bounce of P07 Port
0
Disable
1
Enable
P06DB
Configure De-bounce of P06 Port
0
Disable
1
Enable
P05DB
Configure De-bounce of P05 Port
0
Disable
1
Enable
P04DB
Configure De-bounce of P04 Port
0
Disable
1
Enable
P03DB
Configure De-bounce of P03Port
0
Disable
1
Enable
P02DB
Configure De-bounce of P02 Port
0
Disable
1
Enable
NOTES:
1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.
3. The port de-bounce is automatically disabled at stop mode and recovered after stop mode release.