Abov A96G174 - Page 50

6. I/O ports A96G174/A96S174 User’s manual
50
P1DB (P1 De-bounce Enable Register): DFH
7
6
5
4
3
2
1
0
P17DB
P16DB
P15DB
P14DB
P13DB
P12DB
P11DB
P10DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
P17DB
Configure De-bounce of P17 Port
0
Disable
1
Enable
P16DB
Configure De-bounce of P16 Port
0
Disable
1
Enable
P15DB
Configure De-bounce of P15 Port
0
Disable
1
Enable
P14DB
Configure De-bounce of P14 Port
0
Disable
1
Enable
P13DB
Configure De-bounce of P13 Port
0
Disable
1
Enable
P12DB
Configure De-bounce of P12 Port
0
Disable
1
Enable
P11DB
Configure De-bounce of P11 Port
0
Disable
1
Enable
P10DB
Configure De-bounce of P10 Port
0
Disable
1
Enable
NOTES:
1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.
3. The port de-bounce is automatically disabled at stop mode and recovered after stop mode release.
4. Refer to the port 0 de-bounce enable register (P0DB) for the de-bounce clock of port 1.