Abov A96G174 - Page 7

A96G174/A96S174 User’s manual List of figures
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Figure 48. 16-bit Timer 1 Block Diagram .............................................................................................. 95
Figure 49. 16-bit Timer/Counter Mode of Timer 2 ............................................................................... 100
Figure 50. 16-bit Timer/Counter Mode Operation Example ................................................................ 100
Figure 51. 16-bit Capture Mode of Timer 2 ......................................................................................... 101
Figure 52. 16-bit Capture Mode Operation Example .......................................................................... 102
Figure 53. Express Timer Overflow in Capture Mode ......................................................................... 102
Figure 54. 16-bit PPG Mode of Timer 2 .............................................................................................. 103
Figure 55. 16-bit PPG Mode Operation Example ............................................................................... 104
Figure 56. 16-bit Timer 2 Block Diagram ............................................................................................ 105
Figure 57. 12-bit ADC Block Diagram ................................................................................................. 109
Figure 58. A/D Analog Input Pin with a Capacitor ............................................................................... 109
Figure 59. Control Registers and Align Bits ........................................................................................ 110
Figure 60. ADC Operation Flow Sequence ......................................................................................... 111
Figure 61. I
2
C Block Diagram .............................................................................................................. 114
Figure 62. Bit Transfer on the I2C-Bus ............................................................................................... 115
Figure 63. START and STOP Condition.............................................................................................. 115
Figure 64. Data Transfer on the I2C-Bus ............................................................................................ 116
Figure 65. Acknowledge on the I2C-Bus ............................................................................................. 117
Figure 66. Clock Synchronization during Arbitration Procedure ......................................................... 118
Figure 67. Arbitration Procedure of Two Masters ................................................................................ 118
Figure 68. USART Block Diagram ...................................................................................................... 130
Figure 69. Clock Generation Block Diagram ....................................................................................... 131
Figure 70. Synchronous Mode XCK Timing ........................................................................................ 132
Figure 71. A Frame Format ................................................................................................................. 133
Figure 72. Start Bit Sampling .............................................................................................................. 137
Figure 73. Sampling of Data and Parity Bit ......................................................................................... 138
Figure 74. Stop Bit Sampling and Next Start Bit Sampling ................................................................. 138
Figure 75. SPI Clock Formats when UCPHA = 0 ................................................................................ 140
Figure 76. SPI Clock Formats when UCPHA = 1 ................................................................................ 141
Figure 77. Example for RTO in USART .............................................................................................. 142
Figure 78. 0% Error Baud Rate Block Diagram .................................................................................. 153
Figure 79. IDLE Mode Release Timing by an External Interrupt ........................................................ 155
Figure 80. STOP Mode Release Timing by External Interrupt ............................................................ 156
Figure 81. STOP Mode Release Flow ................................................................................................ 157
Figure 82. Reset Block Diagram ......................................................................................................... 159
Figure 83. Fast VDD Rising Time ....................................................................................................... 160
Figure 84. Internal RESET Release Timing On Power-Up ................................................................. 160
Figure 85. Configuration Timing when Power-on ................................................................................ 161
Figure 86. Boot Process Waveform .................................................................................................... 161
Figure 87. Timing Diagram after RESET ............................................................................................ 163
Figure 88. Oscillator generating waveform example .......................................................................... 163
Figure 89. Block Diagram of LVR ........................................................................................................ 164
Figure 90. Internal Reset at Power Fail Situation ............................................................................... 164
Figure 91. Configuration Timing When LVR RESET........................................................................... 165
Figure 92. LVI Block Diagram ............................................................................................................. 165
Figure 93. Read Device Internal Checksum (Full Size) ...................................................................... 173
Figure 94. Read Device Internal Checksum (User Define Size) ......................................................... 174
Figure 95. Flash Memory Map ............................................................................................................ 176
Figure 96. Address Configuration of Flash Memory ........................................................................... 176
Figure 97. The Sequence of Page Program and Erase of Flash Memory .......................................... 177