Advantech FWA-3260 - Figure 34: Chipset: Processor Configuration Menu; Table 32: Processor Configuration Menu

FWA-3260 User Manual v02_20160302.docx Copyright 2014 Advantech Co. Ltd. All rights reserved. Page 65
Figure 34: Chipset: Processor Configuration Menu
Group
Setup item
Access /
Options
Description
Socket0 CPU
information
CPU signature
Display only
Displays information on the processor
installed
Microcode Patch
CPU Frequency
Processor Cores
Intel VT-x
Technology
L1 code Cache
L2 Cache
L3 Cache
None
Hyper-threading
Enable
Disable
Enables Hyper Threading (Software
Method to enable/disable logical processor
threads.
Execute Disable
Bit
Enable
Disable
Execute Disable Bit allows the processor to
classify areas in memory where application
code can be executed and cannot
preventing certain classes of malicious
buffer overflow attacks when combined with
a supporting operating system.
Hardware
Prefetcher
Enable
Disable
Enable or disable Hardware Prefetcher
feature.
= MLC Streamer Prefetcher (MSR 1A4h
Bit[0])
Adjacent Cache
Line Prefetch
Enable
Disable
Enable or disable Adjacent Cache Prefetch
feature.
= MLC Spatial Prefetcher (MSR 1A4h
Bit[1])
DCU Streamer
Prefetch
Enable
Disable
Enable or disable DCU Streamer
Prefetcher feature.
DCU streamer prefetcher is an L1 data
cache prefetcher (MSR 1A4h [2]).
DCU IP
Prefetcher
Enable
Disable
Enable or disable DCU IP Prefetcher
feature.
DCU IP prefetcher is an L1 data cache
prefetcher (MSR 1A4h [3]).
Table 32: Processor Configuration Menu