Aim ANET42 - 7 Technical Data

7. Technical data
ANET429-x Users Manual
43
7 TECHNICAL DATA
Memory:
DDR2 RAM (Global RAM)
128MByte
LPDDR RAM (ASP Local RAM)
256MByte
SPI-Flash for FPGA Boot
8MByte
SPI-Flash for BIU Processor
1MByte
NAND Flash for ASP Processor
1GByte
BIU-Section:
Low power, high performance 32bit RISC Processor;
core voltage 1.0V, core speed 400 MHz, ext. bus speed 100MHz,
Encoder:
Programmable Bitrate High / Low Speed (100 / 12.5 Kbit/sec)
Programmable gap between two labels in the range from 0 up to
255 ARINC 429 bits.
ARINC429-Label Bit-32 programmable as Parity or additional
Data Bit
Error injection capabilities:
Gap Error (-1 bit)
Bitcount Error (+/- 1 bit)
Coding Error (fixed at bit position 12)
Parity Error (if no special transmission mode is chosen)
Decoder:
Valid Receive Range Transmission speed select +/- appr. 10%
ARINC429-Label Bit-32 programmable as Parity or additional
Data Bit
Measurement of gap between two labels in the range from 0.0 to
58.75 bits with 0.25bit resolution.
Error detection capabilities:
Gap Error Detection
Bitcount Error Detection
Coding Error Detection
Parity Error Detection (if no special transmission mode is
chosen)