Alcatel-Lucent 7210 SAS M Basic System Configuration Guide

System Management
7210 SAS M, X Basic System Configuration Guide Page 163
Central Synchronization Sub-System
The timing subsystem for the 7210 SAS platforms has a central clock located on the CPM
(motherboard). The timing subsystem performs many of the duties of the network element clock
as defined by Telcordia (GR-1244-CORE) and ITU-T G.781.
To train the local oscillator, the system has the option to select from two timing inputs.The priority
order of these references must be specified. This is a simple ordered list of inputs: {ref1, ref2}.
The CPM clock output shall have the ability to drive the clocking for all line cards in the system.
The 7210 SAS supports selection of the node reference using Quality Level (QL) indications. See
Figure 10 for a description of synchronization reference selection.
Figure 10: Synchronization Reference Selection
The recovered clock will be able to derive its timing from any of the following:
• T1/E1 CES channel (adaptive clocking)
• Synchronous Ethernet ports
• T1/E1 port (loop timing)
NOTE: In the current release, Adaptive clocking cannot be used for synchronise the system clock.
It can only be used to supply timing to the T1/E1 ports.
If QL selection mode is disabled, the reversion setting specifies as to when the central clock can
re-select a previously failed reference.
OSSG326
Qualifier
T1/E1,
SONET/SDH,
SyncE,
ACR
Internal
(Node)
Timing
Reference
T1/E1
Quality
Level (QL)
Mode 1)
Priority
Reference Order
Mode 2) QL Then
Priority Reference
Order
BITS - Out
Digital Phase
Locked Loop
(DPLL)
Quality Level
Override
Reference
Selector
Quality
Level (QL)
Quality
Level (QL)
Qualifier
Qualifier
BITSIn
Ref 2
Ref 1
T1/E1
Qualifier
BITSIn
Quality
Level (QL)

Alcatel-Lucent 7210 SAS M Specifications

General

Brand	Alcatel-Lucent
Model	7210 SAS M
Category	Switch
Language	English