ADV7511W HARDWARE USER’S GUIDE
Rev.A
Page 24
of 45
Rev A
Table 8
YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, right justified (R0x48[4:3] = ‘01’)
Input Format
Data<23:0>
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
YCrCB 422 Sep.
Syncs (DDR)
8 bit
Cb[3:0] Y[3:0]
Cb[7:4] Y[7:4]
Cr[3:0] Y[3:0]
Cr[7:4] Y[7:4]
Style 2
8 bit Y[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Style 3
8 bit Cb[7:0]
Y[7:0]
Cr[7:0]
Y[7:0]
An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (R0x15 [3:0]) to 0x6. The three different input pin assignment
styles are shown in the table. The Input Style can be set in R0x16[3:2]. The data bit width (8 bits) must be set with R0x16 [5:4]. The Data Input
Edge is defined in R0x16 [1]. The 1
st
and the 2
nd
edge may be the rising or falling edge. The Data Input Edge is defined in R0x16 [1]. 0b1 = 1
st
edge rising edge; 0b0 = 1
st
edge falling edge. Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts.
Table 9
YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, left justified (R0x48[4:3] = ‘10’)
Input Format
Data<23:0>
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
YCrCB 422 Sep.
Syncs (DDR)
8 bit
Cb[3:0] Y[3:0]
Cb[7:4] Y[7:4]
Cr[3:0] Y[3:0]
Cr[7:4] Y[7:4]
Style 2
8 bit Y[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Style 3
8 bit Cb[7:0]
Y[7:0]
Cr[7:0]
Y[7:0]
An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (R0x15 [3:0]) to 0x6. The three different input pin assignment
styles are shown in the table. The Input Style can be set in R0x16[3:2]. The data bit width (8 bits) must be set with R0x16 [5:4]. The Data Input
Edge is defined in R0x16 [1]. The 1
st
and the 2
nd
edge may be the rising or falling edge. The Data Input Edge is defined in R0x16 [1]. 0b1 = 1
st
edge rising edge; 0b0 = 1
st
edge falling edge. Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts.
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