Analog Devices ADV7511W User Manual

ADV7511W HARDWARE USER’S GUIDE
Rev. A
Page 27
of 45
Rev A
Table 11
illustrates the many audio input and output options that are available with the ADV7511W. Note ‘required’
and ‘optional’ clock notations.
Table 11
Audio input format summary
Input Output
Audio
Select
0x0A[6:4]
Audio
Mode
0x0A[3:2]
I2S Format
0x0C[1:0]
Data Pins Clock Pins Encoding Format Packet Type
000 ** 00 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal
1
Standard I2S Audio Sample Packet
000 ** 01 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Right Justified Audio Sample Packet
000 ** 10 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Left Justified Audio Sample Packet
000 ** 11 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal AES3 Direct Audio Sample Packet
001 00 ** SPDIF Optional: MCLK Biphase Mark
IEC60958 or
IEC61937
Audio Sample Packet
011 00 ** I2S[3:0] Required: MCLK Biphase Mark IEC61937
HBR Audio Stream
Packet
011 01 00 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Standard I2S
HBR Audio Stream
Packet
011 01 01 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Right Justified
HBR Audio Stream
Packet
011 01 10 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Left Justified
HBR Audio Stream
Packet
011 01 11 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal AES3 Direct
HBR Audio Stream
Packet
011 10 ** SPDIF Required: MCLK Biphase Mark IEC61937
HBR Audio Stream
Packet
011 11 00 SPDIF
Required: SCLK
Optional: MCLK
Normal Standard I2S
HBR Audio Stream
Packet
011 11 01 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Right Justified
HBR Audio Stream
Packet
011 11 10 I2S[3:0]
Required: SCLK
Optional: MCLK
Normal Left Justified
HBR Audio Stream
Packet
011 11 11 I2S[3:0] Required: MCLK Normal IEC61937
HBR Audio Stream
Packet
1
Normal Encoding means data is captured on the rising edge of the data clock

Analog Devices ADV7511W Specifications

General

Brand	Analog Devices
Model	ADV7511W
Category	Transmitter
Language	English