Analog Devices ADV7511W

ADV7511W HARDWARE USER’S GUIDE
Rev. A
Page 13
of 45
Rev A
Figure 2
Timing for Video Data Interface
Figure 3 Timing for I2S Audio Interface
t
VSU
Input data:
CLK
Rising Edge
t
VHLD
VHLD
t
VHLD
t
t
VSU
CLK
Dual Edge
Input DDR data:
t
VSU
Valid Data
Valid Data Valid Data
D(23:0), DE,
HSYNC, VSYNC
D(23:0), DE,
HSYNC, VSYNC
t
ASU
Audio data:
I2S[3:0],
LRCLK
SCLK
Rising Edge
t
AHLD
Valid data
R0x0B[6] = 0
t
ASU
SCLK
Falling Edge
Valid data
R0x0B[6] = 1
t
AHLD
Audio data:
I2S[3:0],
LRCLK