ASIX AX99100 User Manual

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Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.1 GPIO and Mode Setting
Table 1-4: GPIO and Mode Setting Pin Description
GPIO and Mode Setting Pins
Pin Name
Type
Pin No
Pin Description
GPIO[23:8]
B5/CU/4m
31, 32,
33, 34,
38, 40,
41, 42,
43, 44,
45, 46,
47, 48,
49, 50
General Purpose I/O signal
GPIO[15:8] are only valid when CHIP_MODE = 100 and 110.
GPIO[23:16] are only valid when CHIP_MODE = 100 and 110 and Port 4 was
disabled by HWCFGEE. Please reference to Section 3.
GPIO7
B5/CU/8m
60
General Purpose Output signal
GPIO7 has an optional function is external wakeup pin in input direction. When
AX99100 entered to L2 mode, this pin can be used to wakeup AX99100 also.
GPIO6
B5/CU/8m
59
General Purpose Output signal
GPIO6 has an optional function is a power-down control signal to power down
the external transceiver when AX99100 entered to L2 mode. This function can be
enabled by setting bit1 and the polarity selection is bit0 in configuration
EEPROM, offset 0x55.
GPIO5/
CHIP_MODE[2]
O5/ 8m
58
General Purpose Output signal when chip exited reset and operating in normal
functional mode.
These pins are input direction during chip reset use to bootstrap the mode setting
to decide the chip operation mode. Please reference to Section 3.1.
GPIO4/
CHIP_MODE[1]
O5/8m
56
GPIO3/
CHIP_MODE[0]
O5/8m
54
GPIO2
O5/8m
53
General Purpose Output signal when chip exited reset and operating in normal
functional mode.
This pin should be connected to the AUX 3.3V in PCIe slot via an external
pull-up resistor. It is used to detect the 3.3V AUX is existed or not.
GPIO1
B5/CU/8m
52
General Purpose I/O signal
GPIO0
B5/CU/8m
51
General Purpose I/O signal
Note: Above GPIO[7:0] are only valid when CHIP_MODE ≠ 000.

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English