ASIX AX99100 User Manual

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Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.7 SPI Interface
Table 1-10: SPI Pin Description
SPI Interface
Pin Name
Type
Pin No
Pin Description
SS[2:0]
O5/4m
41, 40, 34
SPI Slave Select for SPI master.
SS[2:0] is a tri-stateable output, which requires an external pull-up resistor.
SCLK
O5/4m
31
SPI CLocK for SPI master.
SCLK is a tri-stateable output. At Mode 0 or 2, SCLK requires external pull-down
resistor; while at Mode 1 or 3, SCLK requires external pull-up resistor.
MOSI
O5/4m
32
SPI Master Output Slave Input line for SPI master.
When High Speed SPI controller is operating in master module, MOSI is used to
transmit serial data and is a tri-stateable output.
MISO
I5
33
SPI Master Input Slave Output line for SPI master.
When High Speed SPI controller is operating in master module, MISO is used to
receive serial data.
SWAKEn
I5/PU
38
SPI External Wakeup
SWAKEn is external wakeup for SPI interface.
GPIO16
B5/8m
42
General Purpose I/O signal
Note: Above signals are only valid when CHIP_MODE = 100 and 110.

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English