ASIX AX99100 User Manual

ASIX ELECTRONICS CORPORATION Release Date: 06/06/2016
4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX99100
PCIe to Multi I/O Controller
Features
PCI Express
Single-lane (X1) PCI Express End-point
Controller with PHY integrated
Compliant with PCI Express 2.0 Gen 1
Compliant with PCI Express card specifications
Compliant with PCI Power Management 1.2
Supports four PCI Express functions
Supports both legacy and MSI Interrupts
Supports ASPM Power Management
Serial Port Interface
Dual or Quad UARTs
Supports RS-232/RS-422/RS-485
multiprotocol
Bi-directional speeds up to 25 Mbps per port
Full Serial Modem Control
Supports Hardware, Software Flow Control
Supports 5, 6, 7, 8 and 9-bit Serial format
Supports Even, Odd, None, Space and Mark
parity
Supports Custom baud rate by internal PLL or
external clock
Supports On Chip 256 Byte depth FIFOs in
Transmit, Receive path of each Serial Port
Supports remote wakeup and power
management features
Serial Port transceiver shutdown support
Supports Slow IrDA mode (up to 115200bps)
on all Serial Ports
Supports multi-drop application for 9-bit mode
Supports DMA burst transfer
Parallel Port
Compatible with IEEE 1284 – SPP/Byte/ECP
Mode
SPI Master Interface
Programmable SPI clock frequency up to 42MHz
Supports Mode 0, Mode 1, Mode 2 and Mode 3
timing modes
Supports MSB/LSB first transfer fashion
Programmable peripheral chip select, selecting up
to 7 SPI devices
Supports Non-Burst-Type transfer up to 8 bytes
and/or Burst-Type transfer via DMA mode for
high performance
Supports to fragment large data block into several
smaller transfers on SPI bus to reduce software
loading
Supports programmable transfer 0 ~ 8 bytes
OP-Code field in each transfer automatically to
reduce software loading
Supports wakeup by SWAKEn pin from Slave
Local Bus Interface
Supports memory or I/O access through PCIe
BAR0/1 to local bus interface, each BAR
mapping to local bus' chip select (CS0n and
CS1n)
Supports direct access and bus master access
(auto-increment and fixed address)
Supports 8-bit or 16-bit data bus width (little
and big endian bus swap)
Supports up to 2 Kbytes address space and 2
chip select outputs when separated address/data
bus style
Supports up to 64 Kbytes address space and 2
chip select outputs when multiplexed
address/data bus style
Supports programmable local chip select region
Supports “Slave Request based DMA” access
for interfacing with external device with bus
master
Supports clock out, CLKO, up to 62.5MHz
Supports asynchronous or synchronous Local
Bus with required clock output, CLKO
Supports programmable bus access cycles,
self-terminated bus access cycles and
back-to-back turnaround cycles
Supports programmable RSTO, ALE, RDY,
DREQ0/1, DACK0/1, CLKO polarity, and
INT0/1 level/edge trigger
Supports wakeup by INT0/1 and DREQ0/1 pins
Supports I
2
C Master Interface
Up to 24 bi-directional GPIO lines including 8
dedicated GPIO and 16 multi-function GPIO
Integrates on-chip power-on reset circuit
On Chip 3.3 to 1.2V Regulator
68-pin QFN RoHS compliant package
Operating temperature range: 0 to 70°C or -40 to
+85°C
Document No: AX99100/V0.24/06/06/16

ASIX AX99100 Specifications

General

Power Supply	3.3V
Serial Ports	4
Serial Standard	RS-232/422/485
UART	Yes
Parallel Port	1
SPI Master	Yes
I2C Master	Yes
Interface	PCI Express
Operating Temperature	0°C to 70°C
I/O Interfaces	PCI Express
FIFO	128-byte TX/RX FIFO

Summary

Features

PCI Express Features

Details on the PCI Express end-point controller and compliance.

Serial Port Interface Features

Features of the multi-protocol serial ports, speeds, and formats.

Parallel Port Features

Compatibility with IEEE 1284 standards for the parallel port.

SPI Master Interface Features

Specifications for the SPI master controller, timing modes, and transfers.

Local Bus Interface Features

Configuration and access methods for the local bus interface.

I²C Master Interface Features

Features of the I²C master controller and EEPROM loader.

Introduction

General Description

Overview of the AX99100 as a PCIe to Multi I/O controller solution.

AX99100 Block Diagram

Visual representation of the AX99100's internal architecture and interfaces.

AX99100 Pinout Diagram

Diagram showing pin assignments for the 68-pin QFN package.

Signal Description

Explanation of abbreviations and signal types used in pin descriptions.

Function Description

Clocks, Resets, and Power

Details on clock sources, reset mechanisms, and integrated voltage regulator.

PCIe Operation Overview

Explanation of PCIe PHY, Data Link, and Transaction Layers.

I²C Controller Functionality

Functionality of the I²C master and EEPROM loader.

Serial Port (SP) Capabilities

Capabilities of the four serial ports, protocols, and modes.

Parallel Port (PP) Modes

Description of the bidirectional parallel port and its operating modes.

SPI Master Controller Details

Details on the SPI master controller, timing modes, and access types.

Local Bus Controller (LB) Functionality

Functionality of the local bus interface, BARs, and bus modes.

GPIO Functionality

Description of the 24 general-purpose input/output pins and their configuration.

Power Management Features

Features related to PCI Express power management states and wakeup.

Chip Configuration

Boot Strapping Pins for Chip Mode

Explanation of pins used to configure the chip's operating mode at boot.

DTR Boot Strapping Pins for Serial Port

How DTR pins configure serial port modes (RS-232/RS-485).

Hardware Configuration EEPROM

Using an external EEPROM for hardware configuration during boot.

PCIe Configuration Space Map

Mapping of registers within the PCIe configuration space for different functions.

Electrical Specifications

DC Characteristics

Electrical parameters including maximum ratings and operating conditions.

PCIe Specifications

Electrical characteristics specific to the PCIe interface.

Power Consumption

Power consumption details for different interfaces and configurations.

Power-up/down and Power Management Sequence

Sequences for power state transitions and management.

AC Timing Characteristics

Timing specifications for various interfaces like I2C, SPI, and Serial Port.

Package Information

Ordering Information

Revision History