Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
AX99100 Pinout Diagram 1.3
AX99100 is housed in a 68-pin QFN package.
Figure 1-2: AX99100 Pinout Diagram
GPIO0 / CLKO / FAULTn
TXD3 / A4 / DATA0
DTR3 / A5 / DATA1
RTS3 / A6 / DATA2
RXD3 / A7 / DATA3
RI3 / DREQ0 / DATA4
DSR3 / DACK0 / DATA5
DCD3 / DREQ1 / DATA6
CTS3 / DACK1 / DATA7
TXD4 / CS0n / STROBEn
DTR4 / CS1n / AUTOLFn / SS2
RTS4 / ALE / INITn / SS1
VCCIO
RXD4 / RDn / SELECTINn / SWAKEn
VCCK
VCC33A_REG
VO12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CTS1 / AD7
DCD1 / AD6
RI1 / AD4
DSR1 / AD5
RXD1 / AD3
VCCIO
RTS1 / AD2
DTR1 / AD1
TXD1 / AD0
VCCK
DOP
DON
VCC12A_TX
VCC12A_D
DIP
DIN
REXT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RI4 / WRn / ACKn / SS0
DSR4 / RDY / BUSY / MISO
DCD4 / INT0 / PAPEREND / MOSI
CTS4 / INT1 / SELECT / SCLK
SDA
EXT_CLK_PDn
TEST_MODE
SCL
VCCIO
EXT_CLK
RSTn
CLKREQn
VCCK
WAKEn
CLKN
CLKP
VCC12A_AUX
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GPIO1 / RSTO / PP_DIR
GPIO2 / A3
GPIO3 / A2 / CHIP_MODE[0]
VCCIO
GPIO4 / A1 / CHIP_MODE[1]
VCCK
GPIO5 / A0 / CHIP_MODE[2]
GPIO6 / A8
GPIO7 / A9
CTS2 / AD15
DCD2 / AD14
DSR2 / AD13
RI2 / AD12
RXD2 / AD11
RTS2 / AD10
DTR2 / AD9
TXD2 / AD8
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