Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
2 Function Description
Clocks/Resets and Power 2.1
The AX99100 requires an external clock from PCIe connector (CLKP and CLKN) as the main clock source. PCIe
PHY feeds this 100 MHz differential clock to internal PLL to generate the 125MHz clock for PCIe PHY and
Controller or other peripherals used. The AX99100 also supports a clock input from external oscillator for those
special baud rate generated for UART, SPI and Local Bus used if needs. Thus there are three different clock sources
(100Mhz, 125Mhz and EXT_CLK) in this chip can be selected for some interfaces to generate the desired baud rate to
meet the application requirement.
There are two reset sources in the AX99100. During the VCCK power-on, the internal Power-On-Reset (POR) can
generate a reset pulse to reset all the function blocks when the VCCK power pin rise to certain threshold voltage level.
Another reset is RSTn pin, which is from PCIe slot to perform the PCIe Fundamental Reset. If AX99100 is not in L2
power sate, this reset pin will logical and with POR reset to reset all the function blocks also. AX99100 is designed to
meet the PCIe standard for Power Management State.
The AX99100 contains an internal 3.3V to 1.2V low-dropout-voltage regulator. The internal regulator provides up to
150mA of driving current for the 1.2V core and analog power of this chip to satisfy the worst-case power
consumption scenario.
In order to support PCIe power management, all VCCIO power and the regulator power supply should connect to
PCIe Auxiliary Power (3.3Vaux) to maintain the deep sleep and wakeup event.
PCIe Operation 2.2
PCIe is divided into three major blocks as Physical layer, Data link layer and Transaction layer. Physical link layer
and Transaction layer together comprises PCIe core. Their functionality is explained below.
PCIe PHY
The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data
interchange. The Physical Layer is divided into the logical and electrical functional sub-blocks.
The logical sub-block has two main sections: A transmit section that prepares outgoing information passed from the
Data Link Layer for transmission by the electrical sub-block, and a receiver section that identifies and prepares
received information before passing it to the Data Link Layer. The logical sub-block and electrical sub-block
coordinate the state of each transceiver through a status and control register interface or functional equivalent. The
logical sub-block directs control and management functions of the Physical Layer.
The electrical sub-block contains a Transmitter and a Receiver. The Transmitter is supplied by the logical sub-block
with Symbols which it serializes and transmits onto a Lane. The Receiver is supplied with serialized Symbols from
the Lane. It transforms the electrical signals into a bit stream which is de-serialized and supplied to the logical
sub-block along with a Link clock recovered from the incoming serial stream.
The Physical Layer is responsible for the following
Power management
Width and lane negotiation
Reset/hot-plug control
8-bit/10-bit encoding/decoding
Scrambling/de-scrambling
Embedded clock tuning and alignment
Transmission and reception circuit
Elastic buffer
Data Link Layer
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