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AX99100

PCIe to Multi I/O Controller

Local Bus Controller (LB) 2.7

The AX99100’s Local Bus mode provides a PCIe bus target (slave) for adapter boards, in others words, AX99100 can

connect a wide variety local bus design to PCIe bus.

The local bus mode provides four PCIe BARs for access, BAR0 and BAR1 direct mapping to local bus’s chip select

(CS0n and CS1n), configurable with Memory or I/O access with Hardware Configuration EEPROM setting. Software

can use PCIe memory or I/O command through BAR0/1 to access device with local bus directly or active bus master

function (DMA) to transfer large data between PCIe and device. The bus master’s access can be programmed for port

mapping (fixed address) or memory mapping (auto-increment address) also. Another two BARs are BAR4 (I/O

access) and BAR5 (memory access) serve software and driver handle whole PCIe and local bus function. These two

BARs are mapped to same registers to provide local bus access timing adjustment, control pins setting (polarity,

remapping etc.), interrupt control and status response, DMA engine (bus master controller) handling, and I

controller assessment.

The local bus can be configured to asynchronous or synchronous mode, 8 or 16 bits data bus width, data bus

alignment with MSB or LSB when bus width 8 bits and endian type with big or little mode. The address/data of local

bus can be set to Multiplexed or Separated bus type, address/data setup timing, address/data hold timing, address latch

enable timing, read cycle timing and write cycle timing, control pin polarity, and output enable. Above all parameters

can be loaded from EEPROM, and most timing parameters and bus configuration could be adjusted by BAR4/5

related registers too. The BAR0/1 space size could up to 64K Bytes when local bus use address/data multiplex bus

type. If use the separated bus type, the largest size of BAR0/1 are only to 2K Bytes (remapping ALE to A[10]) or 1K

Bytes with ISA bus type (ALE presented access).

The Local Bus of AX99100 also supports clock output (CLKO), which can be configured to generate up to 62.5MHz

with internal 125 MHz clock source or 60MHz with external clock source from EXT_CLK, and reset output (RSTO),

which can be controlled by Software Driver to reset the related off-chip components.

The Local Bus supports address shift feature with local bus shift base register, used for those device with small BAR

space match to local bus with non-zero starting address (like ISA bus device), the chip select also supports starting

address shifting and range resizing feature too.

To enhance the performance, local bus supports “Slave Request based DMA” mode. After software configured

external device and DMA engine was ready, bus master transfer data between PCIe bus and local bus’s device

followed device request to reduce the efforts for the Software checking device status timing.

The Local Bus of AX99100 supports the remote wakeup in L2 power state for PCIe. Application can use INT0/1 and

DREQ0/1 pins to generate the wakeup event to PCIe bus to exit L2 power state.

ASIX AX99100 User Manual

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