ASIX AX99100 User Manual

67
AX99100
PCIe to Multi I/O Controller
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
Symbol
Description
Min
Typ
Max
Units
Clock
Tck
Clock Period
16
-
-
ns
Tck_h
Clock Low Time
-
Tck/2-1
-
ns
Tck_l
Clock High Time
-
Tck/2-1
-
ns
Tck_ris
Clock Rising Time
-
1
-
ns
Tck_fall
Clock Falling Time
-
1
-
ns
Bus Timing
Tcs_dly
Chip Select Delay
0.2
1
ns
Tcs_set
Chip Select Setup Time
Chip Select active to Read/Write active
-0.2
-
Tck/2+0.2
ns
Tcs_hd
Chip Select Hold Time
Write inactive to Chip Select inactive
Tck/2-1.3
-
Tck*DA_
HD
ns
Tale_ctrl
ALE to control active
ALE inactive to read or write active
Tck/4-0.2
-
Tck*DA_S
ET-0.1
ns
Tale_dly
ALE Delay
Tck/4+0.3
-
Tck/4+1
ns
Tale_wd
ALE Width
-
Tck*(ALE_PW+1)
-
ns
Trd_dly
Read Delay
0.1
-
1
ns
Trd_wd
Read Width
-
Tck*(RD_ACC+1) ,
or RDY active,
or RDY timeout
-
ns
Tbrd_wd
Burst Read Width
-
Tck*(BRD_ACC+1)
-
ns
Twr_dly
Write Delay
0.3
-
1
ns
Twr_wd
Write Width
-
Tck*(WR_ACC+1),
RDY active
or RDY timeout
-
ns
Tagap
Access Gap
Tck*(AGAP
+1)
-
-
ns
Ta_dly
Address Delay
-
-
0.5
ns
Tcs_ale
ALE with Chip Select
Chip Select active to ALE inactive
-
Tck/4 + 0.1
-
ns
Ta_set
Address Setup
Address valid to Read/Write active
0.4
Tck*DA_SET
-
ns
Ta_hd
Address hold
Write inactive to Address invalid
Tck/2
-
Tck*DA_
HD
ns
Tadr_set
Address Setup
Address valid to ALE inactive
Tck*(ALE_P
W+3/4)
-
Tck*(ALE
_PW+3/4)
+1.1
ns
Tadr_hd
Address Hold
ALE inactive to Address invalid
Tck/4 - 1.2
-
Tck/4
ns
Tda_dly
Data bus Delay
-0.5
-
0.5
ns
Tdaf
Data Float
Read active to Data bus float
-1.1
-
0.2
ns
Tdwr_set
Data Write Setup
Data valid to Write active
0.4
-
Tck*DA_S
ET
ns
Tdwr_hd
Data Write Hold
Write inactive to Data invalid (bus floating)
Tck/2
-
Tck*DA_
HD
ns
Trdy_set
RDY Setup
0
-
-
ns
Tdak_dly
DACK[1:0] Delay
0
-
0.6
ns
Tint_wd
INT[1:0] Width
Tck*2
-
-
ns
Table 4-2: Local Bus Timing Table

ASIX AX99100 Specifications

General

Brand	ASIX
Model	AX99100
Category	Controller
Language	English