Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Hardware Configuration EEPROM 3.3
AX99100 can use the I
2
C Hardware Configuration EEPROM (HWCFGEE) to overwrite some hardware default
values during boot up if the Configuration EEPROM existed and the checksum is correct. If EEPROM not existed or
checksum uncorrected, Hardware will skip to load the content or give up the loaded values from EEPROM then still
use the hardware default values in each chip mode for the chip operation. It uses a serial EEPROM with I
2
C interface
with at least 256x8 (2048 bits), for example Atmel AT24C02. The 7-bit device address of the I
2
C Hardware
Configuration EEPROM on application circuit must be set to 1010000b. Note that the Hardware will only use the
“8-bit Device Memory Address Format” to load HWCFGEE when boot up.
Following sections show the I
2
C Hardware Configuration EEPROM memory maps with the different layouts between
none Local Bus and Local Bus in EEPROM.
Following are the abbreviations for each interface function for further descriptions.
For those PCIe functions which be configured to support general Serial Ports or Serial Ports with
Multi-Protocol transceivers in Port 1, 2, 3 or 4.
For the PCIe function 3 which be configured to support SPI master in Port 4.
For the PCIe function 2 which be configured to support Parallel Port in Port 3 and 4.
For the PCIe function 0 which be configured to support Local Bus interface.
Note1: Some “Reserved” fields in HWCFGEE may preserve for design optimization. User should use ASIX
provided EEPROM utility to modify or create the new EEPROM contents to avoid the incorrected value to
cause system unstable.
Note2: Boot strapping pins and HWCFGEE will be reloaded in following conditions.
◆ Power OFF (includes 3.3VAUX) then Power ON.
◆ Perform PCIe reset in none L2 state.
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