ASIX AX99100 - SPI Timing; Figure 4-2: High Speed Spi Master

58
AX99100
PCIe to Multi I/O Controller
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
4.5.4 SPI Timing
Symbol
Description
Min
Typ
Max
Units
1
SCLK clock frequency
-
Fsys_clk
SPIBRR
-
MHz
2
Setup time of SS[2:0] to the first SCLK
edge
-
Mode0, 1: (1.0 + DBS) * Tsclk.
Mode2, 3: (0.5 + DBS) * Tsclk.
-
ns
3
Hold time of SS[2:0] after the last SCLK
edge
-
Mode0, 1: (0.5 + DBS) * Tsclk.
Mode2, 3: (1.0 + DBS) * Tsclk.
-
ns
4
Minimum idle time between transfers
(minimum SS[2:0] high time)
-
(2 + DT) * Tsclk.
-
ns
5
MOSI data valid time, after SCLK edge
-
-
2
ns
6
MISO data setup time before SCLK edge
7
-
-
ns
7
MISO data hold time after SCLK edge
0
-
-
ns
8, 9
Bus drive time before SS[2:0] assertion
and after SS[2:0] de-assertion
-
Tsclk
-
Note: Fsys_clk is from 125MHz, 100MHz or EXT_CLK and the SCLK frequency is same as “Desired clock
frequency”. Please reference section 3.3.1, Divide Register. The SPIBRR is SPI Baud Rate Register and same
as N.
Figure 4-2: High Speed SPI Master Controller Timing Diagram and Table
5
4
9
4
3
8
2
7
6
11
SCLK(output)
MOSI(output)
MISO(input)
SS0(output)