104
ATtiny26(L)
1477G–AVR–03/05
• Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits
These bits determine the division factor between the CK frequency and the input clock
to the ADC.
ADC Data Register – ADCL
and ADCH
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. The
ADLAR bit in ADMUX affect the way the result is read from the registers. If ADLAR is
set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. If
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH.
• ADC9..0: ADC Conversion Result
These bits represent the result from the conversion. For differential channels, this is the
absolute value after gain adjustment, as indicated in Table 46 on page 102. For single
ended channels, $000 represents analog ground, and $3FF represents the selected ref-
erence voltage minus one LSB.
Table 47. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
1 1 1 128
Bit 151413121110 9 8
$05 ($25) – – – – – – ADC9 ADC8 ADCH
$04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 151413121110 9 8
$05 ($25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
$04 ($24) ADC1 ADC0 – –––––ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
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