79
ATtiny26(L)
1477G–AVR–03/05
1. In the same operation, write a logical one to WDCE and WDE. A logical one
must be written to WDE even though it is set to one before the disable operation
starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 38.
Note: 1. The frequency of the Watchdog Oscillator is voltage dependent. The WDR – Watch-
dog Reset – instruction should always be executed before the Watchdog Timer is
enabled. This ensures that the reset period will be in accordance with the Watchdog
Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watch-
dog Timer may not start counting from zero.
Table 38. Watchdog Timer Prescale Select
(1)
WDP2 WDP1 WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at V
CC
= 3.0V
Typical Time-out
at V
CC
= 5.0V
0 0 0 16K (16,384) 17.1 ms 16.3 ms
0 0 1 32K (32,768) 34.3 ms 32.5 ms
0 1 0 64K (65,536) 68.5 ms 65 ms
0 1 1 128K (131,072) 0.14 s 0.13 s
1 0 0 256K (262,144) 0.27 s 0.26 s
1 0 1 512K (524,288) 0.55 s 0.52 s
1 1 0 1,024K (1,048,576) 1.1 s 1.0 s
1 1 1 2,048K (2,097,152) 2.2 s 2.1 s
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