BIXOLON SRP-F310 - RESET Circuit

Rev. 1.00
- 40 -
SRP-F310/312
6) FPGA core Voltage: +1.5VDC
Step down voltage the input +2.5VDC to +1.5VDC by a regulation.U16(BH15PB1WHFV-TR)
7) CPU core Voltage: +1.2VDC
Step down voltage the input +24VDC to +1.2VDC by a switching regulation.U13(A4490SES-T)
4-3-2 RESET Circuit
Reset signal is signal in order to start-up CPU under Power-on.
Reset circuit uses a reset ASM811REUSF-T(U8). When 3.3Vdc is fallen under 2.7Vdc by Power-off,
reset signal prohibits the system from miss-operating by lowering down to 0V.
[Figure 4-4 Reset Block Diagram]
[Figure 4-5 Reset Waveform]
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