VFD500 high performance vector control frequency inverter user manual Chapter 5 function code table
DI8 Numeric input
function（option card）
27：Switch main frequency source to AI1
28：Switch main frequency source to AI2
29：Switch main frequency source to AI3
30：Switch main frequency source to AI4
31：Switch main frequency source to high-
frequency pulse input
32：Switch main frequency source to
communication setting
33：Switch auxiliary frequency source to
numeric frequency setting
34：Accel and Decel time terminal 1
35：Accel and Decel time termina2
36：Accel and Decel Stop
37：User-defined fault 1
38：User-defined fault 2
39：PID pause
40：PID integral pause
41：PID parameter Switchover
42：PID Positive/negative reaction switch
43：Preset PID terminal 1
44：Preset PID terminal 2
45：PID Main and Auxaliary command switch
46：PID Main and Auxaliary feedback switch
47：Simple PLC status reset
48：Simple PLC time stop
49：Swing frequency stop
50：Counter 1 input
51：Counter 1 reset/clear
52：Counter 2 input
53：Counter 1 reset/clear
54：Clear/reset timed running time
55：Motor 2 Accel and Decel time selection
DI9 Numeric input
function（option card）
VDI1 Numeric input
function（Virtual DI）
VDI2 Numeric input
function（Virtual DI）
VDI3 Numeric input
function（Virtual DI）
VDI4 Numeric input
function（Virtual DI）
Unit’digit: VDI1 input source
0~F: P06.33 specifies the bit0~bit15 of the
parameter
Ten’s digit: VDI2 input source
0~F: P06.34 specifies the bit0~bit15 of the
parameter.
Hundred’s digit: VDI3 input source
0~F: P06.35 specifies the bit0~bit15 of the
parameter
Thousand’s digit: VDI4 input source
0~F: P06.36 specifies the bit0~bit15 of the
parameter
Define as per bit :Disable;1:Enable
Bit0-bit11:DI1-DI12
Bit12-bit15:VDI1-VDI4
When the bit is enabled, the state of the DI or
VDI is set by the corresponding bit of P06.19.
Define as per bit 0:effective;1:ineffective
Bit0-bit11:DI1-DI12
Bit12-bit15:VDI1-VDI4
Effective logic of
Numericinput terminal
Define as per bit 0:positive logic;1:negative logic
Bit0-bit11:DI1-DI12
Bit12-bit15:VDI1-VDI4
In the reverse logic, the inactive level of the DI
terminal becomes the active level.
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