Delta AH500 - Page 102

Chapter 2 Devices
2-83
latter adopts the decimal system. For example, December is represented as 12 in SR392
while it is represented as 12 in the binary-coded decimal.
Please refer to section 6.17 for more information related to the real-time clock.
4. The functions related to communication
 SM96~SM107, SM209~SM212, SR201~SR202, and SR209~SR216
SR215 and SR216 are used to record the interface code of the communication port on the
PLC. The functions represented by the interface codes are as follows.
Code
0
1
2
Function
RS-232
RS-485
RS-422
When the interface of the communication port on the PLC is RS-485, RS-232, or RS-422,
SR209 records the communication format of COM1 on the PLC, and SR212 records the
communication format of COM2 on the PLC. The setting values of the communication
protocols are shown in the following table. Please refer to section 6.19 for more information
related to the communication instructions.
b0
Data length
7 (value=0)
8 (value=1)
b1
b2
Parity bits
00
:
None
01
:
Odd parity bits
10
:
Even parity bits
b3
Stop bit
1 bit (value=0)
2 bits (value=1)
b4
b5
b6
b7
0001
(16#1)
:
4800
0010
(16#2)
:
9600
0011
(16#3)
:
19200
0100
(16#4)
:
38400
0101
(16#5)
:
57600
0110
(16#6)
:
115200
0111 (16#7) :
230400
RS-232 does not
support the baud rate.
1000 (16#8) :
460800
RS-232 does not
support the baud rate.
1001 (16#9) :
921600
RS-232 does not
support the baud rate.
b8~b15
Undefined (reserved)
5. Clearing the contents of the device
 SM204/SM205
Device number
Device which is cleared
SM204
All non-latched areas are
cleared.
The non-latched areas in the input relays, the output relays, the
stepping relays, the auxiliary relays, and the link registers are
cleared.
The non-latched areas in the timers, the counters, and the
32-bit counters are cleared.
The non-latched areas in the data registers and the index
registers are cleared.
It takes 530 milliseconds to clear the device. The watchdog
timer does not act during this period of time.
SM205
All latched areas are
cleared.
The latched areas in the timers, counters, and 32-bit counters
are cleared.
The latched auxiliary relays are cleared.
The latched data registers are cleared.
It takes 30 milliseconds to clear the device. T
he watchdog timer
does not act during this period of time.
Please refer to section 2.1.4 for more information related to the latched areas in the device
range.
6. The error log in the PLC