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DigiPos PowerPoS User Manual

DigiPos PowerPoS
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DigiPoS PowerPoS & Millennium Technical Manual
Advanced Chipset Features
Phoenix AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Clock [Host CLK]
SDRAM Cycle Length [3]
Bank Interleave [Disabled]
Memory Hole [Disabled]
P2C/C2P Concurrency [Enabled]
System BIOS Cacheable [Disabled]
Video RAM Cacheable [Enabled]
Frame Buffer Size [8M]
AGP Aperture Size [8M]
AGP-4X Mode [Enabled]
AGP Driving Control [Auto]
XAGP Driving Value DA
Disk on Chip Control [Disabled]
Onboard LAN Control [Enabled]
Power Supply Type [AT]
OnChip USB [Enabled]
USB Keyboard Support [Disabled]
OnChip Sound [Auto]
CPU to PCI Write Buffer [Enabled]
PCI Dynamic Bursting [Enabled]
PCI Master 0 WS Write [Enabled]
PCI Delay Transaction [Disabled]
PCI#2 Access #1 Retry [Enabled]
AGP Master 1 WS Write [Disabled]
AGP Master 1 WS Read [Disabled]
Menu Level f
ÇÈÆÅ: Move +/-/PU/PD: Value F10 : Save ESC : Exit F1 : General Help
F5 : Previous Values F6: Fail-Safe Defaults F7 : Optimised Defaults
Details
Feature Options Description
DRAM Clock
Host CLK
HCLK-33M
HCLK+33M
Host CLK = Front Side Bus Speed (FSB)
HCLK-33M = FSB – 33Mhz
HCLK+33M = FSB + 33Mhz
SDRAM Cycle Length
3
2
When synchronous DRAM is installed, the number of
clock cycles of CAS latency depends on the DRAM timing.
Do Not Alter this Setting.
Bank Interleave
Disabled
2 Bank
4 Bank
Set as Disabled
Other options Non-Functional in this BIOS.
Memory Hole
Disabled
15M – 16M
You can reserve this area of system memory for ISA
adapter ROM. When this area is reserved, it cannot be
cached. The user information of peripherals that need to
use this area of system memory usually discusses their
memory requirements.
P2C/C2P Concurrency
Enabled
Disabled
Set as Enabled
Page 52 of 52

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DigiPos PowerPoS Specifications

General IconGeneral
BrandDigiPos
ModelPowerPoS
CategoryTouch terminals
LanguageEnglish

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