DVC DVC-1412 - Figure 7.2-4: HDL Mode

7.2.4.2 High speed shutter with discharge (HDL)
If an asynchronous reset occurs while the camera is in this mode, the residual charge in the storage
area from a previous exposure is flushed out (discharged) by a sequence of vertical channel transfer
pulses. This period lasts for 6.8msec (see timing diagram below). NOTE: the discharge pulses
affect only the storage area; the "charge dump" pulses that are required to clear the imaging area
are generated immediately after the discharge within the 6.8mSec period. This is followed by the
exposure period and then the readout of the integrated charge. As shown below in the timing
diagram, the normal sequence of the Enable_frame signal is interrupted by the asynchronous reset
input; It is forced LOW by the falling edge of the reset signal and remains low until the discharge
and exposure periods are completed (6.8mS + user_defined_shutter_exposure). The rising edge of
the Enable_frame signal signifies the start of the readout process of the synchronized frame.
NOTE: the Enable_line and Pixel Clock signals are un-interrupted by the reset signal and run
continuously.
NOTE: If the exposure period is greater than 80 lines, then a special condition exists, which
allows a concurrent discharge and exposure, eliminating the taking period between the falling edge
of reset and the start of exposure that exists in cases where the exposure period is less than 80 lines.
After the synchronized frame is readout, normal shutter operation resumes until the next falling
edge of the asynchronous reset is received.
VRST_INT (TTL) or INPUT1 (LVDS)
Enable_frame
Pixel Clock and Enable_Line (run continuously)
STROBE OUT (TTL)
READOUT
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Discharge duration = 6.8ms
User defined
exposure period
1 frame =
1/10 sec
Figure 7.2-4: HDL mode
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