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ETM62E-02 Seiko Epson Corporation 25
Figure 19 Basic Function 32.768 kHz oscillation, counter, FOUT
14.1. Clock Calendar Explanation
Table 16 Time Calendar setting Ex.
Note
With caution that writing non-existent time data may interfere with normal operation of the clock counter
Time starts at the moment of STOP bit operation (1 to 0 timing)
14.1.1. Clock Counter
1) [SEC],[MIN]register
These registers are 60-base BCD counters. When update signals were generated from a lower counter, a upper counter is one
incremented. At the timing when the lower register changes from 59 to 00, carry is generated to the higher register and thus
incremented.
When writing is performed to [SEC] register, Internal-count-down-chain less than one second (512 Hz1Hz) is cleared to 0.
2) [HOUR]register
This register is a 24-base BCD counter (24-hour format). These registers are incremented at the timing when carry is generated
from a lower register.
3) Leap second adjustment
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