RX4111CE Jump to Top / Bottom
ETM62E-02 Seiko Epson Corporation 33
3) AF bit(Alarm Flag)
When this flag bit value is already set to 0, occurrence of an alarm interrupt event changes it to 1. When this flag bit value is 1,
its value is retained until a 0 is written to it.
Table 30 AF bit (Alarm Flag)
Clearing this bit to zero enables /INT low output to be canceled (/INT remains
Hi-z) when an alarm interrupt event has occurred
Invalid (writing a 1 will be ignored)
Alarm interrupt events are not detected.
Alarm interrupt events are detected.
(Result is retained until this bit is cleared to zero.)
4) AIE bit(Alarm Interrupt Enable)
This bit is used to control output of interrupt signals from the /INT pin when an Alarm interrupt event has occurred.
Table 31 AIE bit (Alarm Interrupt Enable)
1) The Alarm interrupt signal is not output.
2) The Alarm interrupt signal during output is immediately released.
Note. as for INT-pin, Alarm, Wake-up Timer and Time update interrupts are
output as OR.
When an Alarm interrupt event
/INT status changes from Hi-z to low
The AIE bit is only output control of the /INT pin. It is necessary to clear an AF flag to cancel alarm.
14.3.2. Examples Of Alarm Settings
1) Example of alarm settings when "Week" has been specified (and WADA bit=0)
Table 32 Alarm Setting Ex1.
Hour value is ignored
2) Example of alarm settings when "Day" has been specified (and WADA bit=1)
Table 33 Alarm Setting Ex2.
WADA bit = 1
To Next Page
Loading...
