Epson RX4111CE - Figures

17.Figures
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RX4111CE Jump to Top / Bottom
ETM62E-02 Seiko Epson Corporation 59
Table 60 EDVET bit (Enable VDET) ................................................................................................................47
Table 61 EXST bit ............................................................................................................................................47
Table 62 Time Stamp RAM control registers ...................................................................................................47
Table 63 TSRAM bit (Time Stamp RAM) .........................................................................................................48
Table 64 TSCLR bit ..........................................................................................................................................49
Table 65 EISEL bit (Event Interrupt Select) .....................................................................................................49
Table 66 TSFUL bit ..........................................................................................................................................49
Table 67 Time Stamp Empty bit .......................................................................................................................49
Table 68 TSAD bit ............................................................................................................................................49
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Figure 1 Block Diagram ......................................................................................................................................5
Figure 2 Package Pin Layout .............................................................................................................................6
Figure 3 Circuit Ex.1 ...........................................................................................................................................7
Figure 4 Circuit Ex.2 ...........................................................................................................................................7
Figure 5 Circuit Ex.3 ...........................................................................................................................................7
Figure 6 Circuit EX.4 ..........................................................................................................................................7
Figure 7 External dimensions.............................................................................................................................8
Figure 8 Marking layout ......................................................................................................................................8
Figure 9 Chargeable current of VBAT (VDD = 3.0 V) ......................................................................................11
Figure 10 Chargeable Current of VBAT (VDD = 5.5V) ....................................................................................11
Figure 11 Circuit of charge to Re-chargeable Battery .....................................................................................11
Figure 12 SPI-Bus Timing Chart ......................................................................................................................12
Figure 13 Power on Sequence ........................................................................................................................13
Figure 14 VDD, CE sequence ..........................................................................................................................14
Figure 15 Oscillation start time chart (Power initial supply) .............................................................................14
Figure 16 Recovery from Backup ....................................................................................................................15
Figure 17 Frequency vs Temperature characteristics .....................................................................................16
Figure 18 Basic Function 32.768 kHz oscillation, counter, FOUT ...................................................................25
Figure 19 Wake-up Timer Initial Sequence (cycle error) .................................................................................27
Figure 20 Wake-up Timer Block Diagram (timer source) ................................................................................28
Figure 21 Wake-up Timer Start Sequence ......................................................................................................30
Figure 22 Wake-up Timer Block Diagram ........................................................................................................31
Figure 23 Wake-up Timer Timing Chart...........................................................................................................31
Figure 24 Alarm Interrupt Black Diagram ........................................................................................................34
Figure 25 Alarm Interrupt Timing Chart ...........................................................................................................34
Figure 26 Time Update Interrupt Block Diagram .............................................................................................36
Figure 27 Time Update Timing Chart ...............................................................................................................36
Figure 28 Battery Backup Switchover Function Block Diagram ......................................................................39
Figure 29 Battery backup switchover control (Initial power on) .......................................................................40
Figure 30 Battery backup switchover control (INIEN:1) ...................................................................................41
Figure 31 VDD voltage detection SW OFF intermittent operation ...................................................................42
Figure 32 Time Stamp function ........................................................................................................................43
Figure 33 OVW, pointer operation ...................................................................................................................44
Figure 34 Time Stamp SPI-Bus record timing .................................................................................................45
Figure 35 Time stamp recording registers .......................................................................................................46
Figure 36 Careful timing process for VDET, XST time stamp .........................................................................48
Figure 37 Mixed usage of USER RAM and Time stamp RAM ........................................................................48
Figure 38 Flow1 ................................................................................................................................................50
Figure 39 Flow2 ................................................................................................................................................51
Figure 40 Flow3 ................................................................................................................................................52
Figure 41 Flow4 ................................................................................................................................................52
Figure 42 Flow5 ................................................................................................................................................53
Figure 43 Flow6 ................................................................................................................................................53
Figure 44 Flow7 ................................................................................................................................................54
Figure 45 Flow8 ................................................................................................................................................55
Figure 46 Typical MCU connection example ...................................................................................................57