154 / 266 3CIRCUIT DESCRIPTION
in time. For this possibility, in which the logic might operate undefined, a "Power-on time-delay circuit"
avoids undefined starting of the output stage transistor.
With transistor T11, the supply voltage VDD = + 15 V is monitored. If this voltage is missing, capacitor C10
is quickly discharged via diode D12. This logical LO signal is sent to the two NAND gates ½ IC 1 and
blocks the starting pulses. If the supply voltage is present, capacitor C10 is charged to 15 V via transistor
T11 and resistor R8 in a predefined delay time. This HI signal reaches the two NAND gates again (see
above) and enables the start pulses for the output stage.
On the secondary side of the driver transformers, short, steep spikes occur, initially a positive pulse for
starting, then a negative pulse for stopping the corresponding output stage transistor.
These spikes reach the gates of the MOS-FET transistors via the clamping circuit described above, and
switch the gates.
The amplified output signal is tapped at the two mutual connection points of the transistors.
QC power stage
Slot J4
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