Evalue Technology ECM-3610 - Advanced Chipset Features; Chipset Features Overview; DRAM Timing and Clock Settings

User’s Manual
58 ECM-3610/3610L User’s Manual
4.5.4 Advanced Chipset Features
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if
data is being lost. Such a scenario might well occur if your system had mixed speed
DRAM chips installed so that greater delays may be required to preserve the integrity of
the data held in the slower memory chips.
4.5.4.1 DRAM Timing by SPD
This item allows you to select the SDRAM timing value by SPD data.
The Choice: Enabled, Disabled.
4.5.4.2 DRAM Clock
This item allows you to set DRAM clock speed.
The Choice: Host CLK, HCLK-33M, HCLK+33M.