User’s Manual
6 ECM-3610/3610L User’s Manual
2.3.1 VIA Eden™ Processor
The VIA C3 processor in Enhanced Ball Grid Array (EBGA) packaging is based upon a
unique internal architecture and is manufactured using advanced 0.15μ or 0.13μ CMOS
technology. The C3 architecture and process technology provide a highly compatible,
high-performance, low-cost, and low-power solution for the desktop PC, notebook, and
Internet Appliance markets. The VIA C3 processor in EBGA is available in several MHz
versions.
When considered individually, the compatibility, function, performance, cost, and power
dissipation of the VIA C3 processor family are all very competitive. Furthermore, the value
added from the advanced EBGA packaging includes remarkable compactness, cost
efficiency and excellent thermal characteristics. The VIA C3 package in EBGA represents
a breakthrough combination for enabling high-value, high-performance, low-power, small
form factor x86-based solutions. When considered as a whole, the VIA C3 processor
family in EBGA offers a peerless level of value.
n Enables flexible & innovative system designs
l Desktop & mobile devices
l Small, low profile form factors
l Fanless implementation for ergonomic silent designs
n Optimizes heat dissipation & power consumption
l Saves energy costs
l Ensures longer battery life in mobile designs
l Enhances reliability, particularly for “always on” designs
2.3.2 VIA VT8606 North Bridge
TwisterT (VT8606) is a high performance, cost-effective and energy efficient SMA chip set
for the implementation of mobile personal computer systems with 66 MHz, 100 MHz and
133 MHz CPU host bus (“Front Side Bus”) frequencies and based on 64-bit Socket-370
(VIA Cyrix III and Intel Celeron and Tualatin) and Slot-1 (Intel Pentium III) super-scalar
processors. TwisterT integrates VIA’s VT82C694T system controller, S3’s Savage4 2D/3D
graphics accelerator and S3’s flat panel interfaces into a single 552 BGA package. The
TwisterT SMA system controller provides superior performance between the CPU, DRAM
and PCI bus with pipelined, burst, and concurrent operation.
TwisterT supports six banks of DRAMs (three memory modules) up to 1.5Gbyte of system
memory with 256Mbit DRAM technology. The DRAM controller supports standard
Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible
mix / match manner. The Synchronous DRAM interface allows zero wait state bursting
between the DRAM and the data buffers at 100 / 133 MHz. The six banks of DRAM can
be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The
DRAM controller can run at either the host CPU Front Side Bus frequency (100 / 133 MHz)
or pseudo-synchronous to the CPU FSB frequency (PC100 with the FSB at 133 MHz or
PC133 with the FSB at 100 MHz) with built-in PLL timing control.
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