User’s manual FlexGain Plex, V2
Version 1.3 17 from 99
The converted signal is transmitted to input framers 6 and 42, which perform the
following:
• searches clock symbols in the input stream;
• buffers and equates data in this stream;
• verifies data by calculating and checking CRC4 check sums for each E1
multiframe;
• separates national Sa bits from the streams.
Cross-connect matrix 7 is connected to outputs of framers 6 and 42, which
distributes the time slots of the received E1 stream between V.35 framer 12 and interfaces
of daughter boards 14 and 16. By using input 18 and output 19 mixers, the cross-connect
matrix is coupled to unit 20 of fast signal processing. Unit of fast signal processing 20 is
based on a highly efficient digital signal processor (DSP) and is used to:
• analyse zeroth time slots of input E1 streams to separate national Sa bits;
• form a sequence of national Sa bits, which are transmitted then to the output
framer;
• analyse time slots carrying signaling (by default TS No.16) of the input stream
to separate the incoming telephone signaling of voice interfaces P1-P8 (in
PCM-30 and PCM-30C modes);
• form a bit sequence of the outcoming telephone signaling of voice interfaces
P1-P8 (in PCM-30 and PCM-30C modes).
The daughter board RINGER is a ring generator for FXS units (daughter boards 15
and 17). The electric and mechanic coupling of the board RINGER with the basic
motherboard of the multiplexer is provided with the help of an interface of daughter board
8.
The common management of the device units and their performance control is
performed by central ARM processor 29. The management is performed in accordance
with the downloaded software and current configurations. The software and configurations
are stored in nonvolatile FLASH ROM 36. The live data are stored in RAM 35. The
processor also tracks the appearance of alarm conditions. If alarm conditions appear,
commands are sent to cross-connect 34, which manages warning relay 33. Clock 30 is
used to trace the date and current time. Display unit 28 consisting of 12 LEDs shows the
device statuses and statuses of its interfaces. The display unit is managed by the central
processor. Information in the multiplexer is processed by clock synchronization. There can
be the following clock sources:
• a signal recovered from the E1 stream;
• external clock source 22;
• internal clock 27.
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