User’s manual FlexGain Plex, V2
Version 1.3 29 from 99
1.10.2 Е1 clock.
The E1 mode. In this case, a clock recovered from any received stream of the E1
port is used (PCM1 or PCM2). When this clock is used, the E1 LED is lit red and an urgent
alarm is displayed. This mode is configured by the <SETCLOCK PCM1> or <SETCLOCK
PCM2> commands in the CONFIGURATION MANAGEMENT menu.
1.10.3 External clock.
The EXTERNAL mode. In this case, a clock from the external generator is used,
whose parameters correspond to ITU-T Rec. G.703.10. Synchronization from the external
source in Mini-Rack devices is possible, if the clock signal is fed to the input «2048 kHz
IN». External synchronization in Sub-Rack devices is possible if it is installed together with
ACU or CMU units in the same shelf and the clock signal is fed to its input «2048 kHz IN».
If the external clock fails, the INTERNAL clock source is used by the FlexGain Plex, V2
device. This mode is configured by the <SETCLOCK EXT> command in the
CONFIGURATION MANAGEMENT menu.
1.11 V.35 clock.
There exist two type of synchronization of the V.35 interface: codirectional and
contradirectional synchronization. The multiplexer interface always plays the role of the
DCE interface, i.e., the interface of the data transmission device. To synchronize
information transmitted from DCE to DTE along the 104 circuit, a signal transmitted from
DCE to DTE along the 115 circuit is always used. The information synchronization mode
transmitted from DTE to DCE along the 103 circuit, is determined by the user. If a signal
transmitted from DTE to DCE along the 113 circuit is used for synchronization, this mode is
called codirectional synchronization. This mode is activated by the <V35CLKMODE
CODIR> command. If a signal transmitted from DCE to DTE along the 114 circuit is used
for synchronization, this mode is called contradirectional synchronization. This mode is
activated by the <V35CLKMODE CONTRDIR> command. Apart from these types of
synchronization, the user has an option to select the element of the clock signal (the clock
leading edge or the clock trailing edge). There are two commands to realize this option for
circuits 113 and 114, respectively, i.e., <V35CLKRX> и <V35CLKTX>. The use of these
commands with the parameter NORMAL sets synchronization from the clock leading
edges. The use of these commands with the parameter INVERS sets synchronization from
the clock trailing edges.
The scheme of synchronization of the V.35 interface is presented in Fig. 6.