2-18
3. Function and overview of each board
MODEM circuitMODEM circuit
MODEM circuitMODEM circuit
MODEM circuit
The DSC reception signal (AFSK signal) is input to the MODEM circuit from the DSC watch keeping
receiver PCB and the DSC general watch keeping receiver PCB (MF/HF radiotelephone if the DSC
general watch keeping receiver PCB is not present).
The signal, having a frequency of 1700Hz +85Hz, 100bps, and 0dBm +10dBm, is input to the
CODEC, U12 through a buffer and a limiter.
The CODEC consists of A/D and D/A converters. In receiving, analog information of the AFSK signal
is converted into digital, and in sending, digital information is converted into analog information of
AFSK signal.
If the DSC signals are input from both ports, the message has higer priority is displayed, and the other
message is printed out and stored in the receive message memory (RX LOG).
The DSC digital signal output from the CODEC starts with dot pattern and sync sequence, and the
message consists of 7 bits data and 3 bits parity. Bit sync, character sync, and error check are performed
in the U13, DSP.
DSC signal in scan receiving is detected in dot pattern, and synchronized in sync sequence. Minimum
signal required for the synchronization is 3 characters of DX and RX. That is, time is required more
than 30 msec. When scanning is stopped, sync can be taken only by sync sequence. Scan time is 270
msec per frequency.
Serial communication is applied between the DSP and main CPU. 7 bit DSC data is converted to 8 bits,
and sent to the main CPU in hexadecimal digit. The CPU decodes this data, displays it on the LCD if it
relates to its own ship, and sounds the alarm.
An edited DSC message is sent to the DSP and CODEC from the main CPU. The CODEC is output by
the signal of 1700Hz +85Hz 100bps, amplifier circuit, and is input to the MF/HF radiotelephone by a
signal of 0dBm as DSC line output.
Synchronized
DX/RX Phasing sequence
DX DX DX DX DX DX
RX RX RX RX RX RX
RX
RX
01234567
(BY----BY)
Dot Pattern
MSG.
DSC sequence diagramDSC sequence diagram
DSC sequence diagramDSC sequence diagram
DSC sequence diagram
Note: In dot pattern, SCAN is stopped
in SCAN reception, and sync is taken
by DX/RX.
MODEM cirMODEM cir
MODEM cirMODEM cir
MODEM cir
cuit bcuit b
cuit bcuit b
cuit b
locloc
locloc
loc
k diak dia
k diak dia
k dia
gg
gg
g
rr
rr
r
amam
amam
am
DSP
MAIN CPU
Sport1
FL0
RFS0
SCLK0
Sport0
ADSP2181KST-115
Reset
SIO-0
Program RAM:16kW
DATA RAM:16kW
FR30
S DATA
BIT-CLK
SYNC
Lin-L
Lin-R
Lout-L
CODEC
AD1819BJST
Limiter
1SS226
Limiter
1SS226
NJM4558M
Buff AMP
Buff AMP
Buff AMP
NJM4558M
NJM4558M
Line AMP
NJM3404AM
U13 U12
(MB91101)
U3
U58
U57
U56
CR42
CR41
U55
AFSK
AFSK
AFSK
MAIN Program
Flash ROM
U11
DSP Program
Flash ROM
U4
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