GW Instek PSW Series - Parallel; Series Operation

PSW Series User Manual
72
Status Byte Register & Service Request Enable Register
Overview
The Status Byte register consolidates the status
events of all the status registers. The Status Byte
register can be read with the *STB? query or a
serial poll and can be cleared with the *CLS
command. When a serial poll is executed the
RQS bit generates a service request. A serial
poll will not clear any of the Status byte
registers.
An *STB query will ready the status byte
register with the MSS bit, not the RQS bit.
MSS
ERR
QUES
MAV
ESB
RQS
OPER
0
1
2
3
4
5
6
7
Service
Request
Generation
Output
Buffer
:
:
:
Error Que
:
:
:
Status
Byte
Register
6
0
1
2
3
4
5
6
7
&
&
&
&
&
&
&
*SRE <NRf>
*SRE?
Service
Request
Enable
Register
Logical OR
*STB?
From Operation
Status Register
From
Questionable
Status Register
From Standard
Event Status
Register
Bit Summary
Event Bit #
Bit
Weight
ERR (Error Event/Queue)
If data is present in the Error
queue, the ERR bit will be set.
2 4