42
Depending on what is being used to assert the Aux A input, there are multiple methods available to derive the A Input Delay
setting value.
A Input Assertion Methods to Derive A INPUT DELAY Setting
1
Parallel connection to “Red
Light” or trip initiate contacts
• Use breaker trip trace, A Input Delay setting is the time difference between
the trip initiate signal and the parting of the main contacts
• Use ANSI C37.06 to approximate latch release times based on kV level of
breaker if a breaker trip trace is unavailable
2
Parallel connection to 52 / a
contact in breaker trip circuit
• Use breaker trip trace, A Input Delay setting is the time difference between
the opening of the 52 / a contact and the parting of the main contacts
• Use breaker operation time line provided by the manufacturer in Instruction
literature, provided the 52 / a contact has not been adjusted from the
manufacturer
3 Parallel connection to Trip Coil
• Use breaker trip trace, A Input Delay setting is the time difference between
the opening of the 52 / a contact and the parting of the main contacts
• Use breaker operation time line provided by the manufacturer in Instruction
literature, provided the 52 / a contact has not been adjusted from the
manufacturer
4
Series connection to wetted
52 / a contact not in breaker
trip circuit
• Use breaker trip trace, A Input Delay setting is the time difference between
the opening of the 52 / a contact and the parting of the main contacts
• Use breaker operation time line provided by the manufacturer in Instruction
literature, provided the 52 / a contact has not been adjusted from the
manufacturer
5
Use of auxiliary relay in
conjunction with method 1
• Same as method 1, but the delay in pick-up or drop out of the auxiliary relay
(depending on application) must be added or subtracted from the A Input
Delay time setting
6
Use of another input that
indexes the trip initiate
contacts
• Same as method 1, but the delay in pick-up or drop out of the initiating input
(depending on application) must be added or subtracted from the A Input
Delay time setting
Table 5: Impact of A Input Assertion on the A Input Delay Setting
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