Thermal/Mechanical Reference Design
16 Dual-Core Intel® Xeon® Processor 5100 Series Thermal/Mechanical Design Guide
circuit. This data set is then used to derive the TDP targets published in the processor
Datasheet. The Thermal Monitor can protect the processor in rare workload excursions
above TDP. Therefore, thermal solutions should be designed to dissipate this target
power level. The thermal management logic and thermal monitor features are
discussed in extensive detail in the Dual-Core Intel
®
Xeon
®
Processor 5100 Series
Datasheet.
In addition, on-die thermal management features called THERMTRIP# and FORCEPR#
are available on the Dual-Core Intel Xeon Processor 5100 Series. They provide a
thermal management approach to support the continued increases in processor
frequency and performance. Please see the Dual-Core Intel
®
Xeon
®
Processor 5100
Series Datasheet for guidance on these thermal management features.
2.2.2 Digital Thermal Sensor
The Dual-Core Intel Xeon Processor 5100 Series introduce a new on-die temperature
sensor known as the Digital Thermal Sensor (DTS) that replaces the Tdiode in previous
products.
The DTS uses the same sensor utilized for TCC activation. Each individual processor is
calibrated so that TCC activation occurs at a DTS value of 0°C. The temperature
reported by the DTS is the number of degrees below the TCC activation temperature
(i.e below 0°C), and is always negative. For example, -10 reported by DTS means 10°C
away from the TCC activation. No value above the TCC activation temperature (that is,
above 0°C) will be reported, DTS will simply report 0.
The DTS utilizes a thermal sensor that is optimally located when compared with
thermal diodes available with legacy processors. This is achieved as a result of a
smaller foot print and decreased sensitivity to noise.
The DTS also facilitates the use of multiple thermal sensors within the processor
without the burden of increasing the number of thermal sensor signal pins on the
processor package. With the legacy thermal diode, each thermal sensor required
dedicated signal pins. Operation of multiple DTS will be discussed more detail in
Section 2.2.4.
The DTS benefits will be realized in more accurate fan speed control and TCC
activation. The DTS application in fan speed control will be discussed more detail in
Section 2.3.1.
2.2.3 Platform Environmental Control Interface (PECI)
The PECI interface is designed specifically to convey system management information
from the processor (initially, only thermal data from the Digital Thermal Sensor). It is a
proprietary single wire bus between the processor and the chipset or other health
monitoring device. Data from the Digital Thermal Sensors are processed and stored in
a processor register (MSR) which is queried through the Platform Environment Control
Interface (PECI). The PECI specification provides a specific command set to discover,
enumerate devices, and read the temperature. For an overview of the PECI interface,
please refer to PECI Feature Set Overview. For more detail information on PECI, please
refer to Platform Environment Control Interface (PECI) Specification and Dual-Core
Intel
®
Xeon
®
Processor 5100 Series Datasheet.
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