Intel Xeon E5-2600 Series - Page 5

Reference Number: 327043-001 5
Figures
1-1 Uncore Sub-system Block Diagram of Intel Xeon Processor E5-2600 Family ................9
1-2 Perfmon Control/Counter Block Diagram...............................................................11
Tables
1-1 Per-Box Performance Monitoring Capabilities.........................................................10
1-2 MSR Space Uncore Performance Monitoring Registers.............................................12
1-3 PCICFG Space Uncore Performance Monitoring Registers ........................................13
2-1 UBox Performance Monitoring MSRs.....................................................................19
2-2 U_MSR_PMON_CTL{1-0} Register – Field Definitions .............................................20
2-3 U_MSR_PMON_CTR{1-0} Register – Field Definitions.............................................20
2-4 U_MSR_PMON_FIXED_CTL Register – Field Definitions ...........................................21
2-5 U_MSR_PMON_FIXED_CTR Register – Field Definitions...........................................21
2-8 CBo Performance Monitoring MSRs ......................................................................24
2-9 Cn_MSR_PMON_BOX_CTL Register – Field Definitions ............................................27
2-10 Cn_MSR_PMON_CTL{3-0} Register – Field Definitions............................................27
2-11 Cn_MSR_PMON_CTR{3-0} Register – Field Definitions ...........................................28
2-12 Cn_MSR_PMON_BOX_FILTER Register – Field Definitions........................................29
2-13 Opcode Match by IDI Packet Type for Cn_MSR_PMON_BOX_FILTER.opc ...................29
2-33 HA Performance Monitoring MSRs........................................................................46
2-34 HA_PCI_PMON_BOX_CTL Register – Field Definitions .............................................47
2-35 HA_PCI_PMON_CTL{3-0} Register – Field Definitions.............................................47
2-36 HA_PCI_PMON_CTR{3-0} Register – Field Definitions ............................................48
2-37 HA_PCI_PMON_BOX_OPCODEMATCH Register – Field Definitions............................48
2-38 HA_PCI_PMON_BOX_ADDRMATCH1 Register – Field Definitions...............................48
2-39 HA_PCI_PMON_BOX_ADDRMATCH0 Register – Field Definitions...............................49
2-59 iMC Performance Monitoring MSRs.......................................................................60
2-60 MC_CHy_PCI_PMON_BOX_CTL Register – Field Definitions......................................60
2-61 MC_CHy_PCI_PMON_CTL{3-0} Register – Field Definitions .....................................61
2-62 MC_CHy_PCI_PMON_FIXED_CTL Register – Field Definitions ................................... 62
2-63 MC_CHy_PCI_PMON_CTR{FIXED,3-0} Register – Field Definitions ...........................62
2-73 PCU Performance Monitoring MSRs ......................................................................72
2-74 PCU_MSR_PMON_BOX_CTL Register – Field Definitions ..........................................73
2-75 PCU_MSR_PMON_CTL{3-0} Register – Field Definitions..........................................74
2-76 PCU_MSR_PMON_CTR{3-0} Register – Field Definitions .........................................75
2-77 PCU_MSR_PMON_BOX_FILTER Register – Field Definitions......................................76
2-78 PCU_MSR_CORE_C6_CTR Register – Field Definitions.............................................76
2-79 PCU_MSR_CORE_C3_CTR Register – Field Definitions.............................................76
2-80 PCU Configuration Examples...............................................................................77
2-84 Intel® QPI Performance Monitoring Registers........................................................88
2-85 Q_Py_PCI_PMON_BOX_CTL Register – Field Definitions..........................................89
2-86 Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions..........................................89
2-87 Q_Py_PCI_PMON_CTR{3-0} Register – Field Definitions .........................................90
2-88 Q_Py_PCI_PMON_PKT_MATCH1 Registers.............................................................91
2-89 Q_Py_PCI_PMON_PKT_MATCH0 Registers.............................................................91
2-90 Q_Py_PCI_PMON_PKT_MASK1 Registers...............................................................92
2-91 Q_Py_PCI_PMON_PKT_MASK0 Registers...............................................................92
2-92 Message Events Derived from the Match/Mask filters..............................................93